gcc/ChangeLog:
* config.gcc: Include intrin file.
* config/i386/i386-builtin-types.def:
Define V16QI_FTYPE_V8BF, V16QI_FTYPE_V16BF, V16QI_FTYPE_V32BF,
V16QI_FTYPE_V8HF, V16QI_FTYPE_V16HF, V16QI_FTYPE_V32HF,
V16QI_FTYPE_V8BF_V8BF, V16QI_FTYPE_V16BF_V16BF,
V32QI_FTYPE_V32BF_V32BF, V16QI_FTYPE_V8HF_V8HF,
V16QI_FTYPE_V16HF_V16HF, V32QI_FTYPE_V32HF_V32HF,
V16QI_FTYPE_V16QI_V8BF, V16QI_FTYPE_V32QI_V16BF,
V16QI_FTYPE_V64QI_V32BF, V16QI_FTYPE_V32QI_V16HF,
V16QI_FTYPE_V64QI_V32HF.
* config/i386/i386-builtin.def
(BDESC): Handle AVX10_INT4_FP4 builtins.
* config/i386/i386-expand.cc (ix86_expand_args_builtin):
Handle V16QI_FTYPE_V8BF, V16QI_FTYPE_V16BF, V16QI_FTYPE_V32BF,
V16QI_FTYPE_V8HF, V16QI_FTYPE_V16HF, V16QI_FTYPE_V32HF,
V16QI_FTYPE_V8BF_V8BF, V16QI_FTYPE_V16BF_V16BF,
V32QI_FTYPE_V32BF_V32BF, V16QI_FTYPE_V8HF_V8HF,
V16QI_FTYPE_V16HF_V16HF, V32QI_FTYPE_V32HF_V32HF,
V16QI_FTYPE_V16QI_V8BF, V16QI_FTYPE_V32QI_V16BF,
V16QI_FTYPE_V64QI_V32BF, V16QI_FTYPE_V32QI_V16HF,
V16QI_FTYPE_V64QI_V32HF.
* config/i386/immintrin.h: Include avx10_3int4fp4intrin.h.
* config/i386/sse.md (UNSPEC_VCVT2BF162BF4S): New.
(UNSPEC_VCVT2BF162SNS): Ditto.
(UNSPEC_VCVT2BF162UNS): Ditto.
(UNSPEC_VCVTBF162BF4S): Ditto.
(UNSPEC_VCVTBF162SNS): Ditto.
(UNSPEC_VCVTBF162UNS): Ditto.
(UNSPEC_VCVT2PH2BF4S): New.
(UNSPEC_VCVT2PH2SNS): Ditto.
(UNSPEC_VCVT2PH2UNS): Ditto.
(UNSPEC_VCVTPH2BF4S): Ditto.
(UNSPEC_VCVTPH2SNS): Ditto.
(UNSPEC_VCVTPH2UNS): Ditto.
(UNSPEC_VCVTBIASBF162BF4S): Ditto.
(UNSPEC_VCVTBIASPH2BF4S): Ditto.
(ssebvecmode): Add V8BF/V16BF/V32BF.
(ssebvecmode_2): Ditto.
(UNSPEC_2F16CVTINT4FP4_ITER): New.
(UNSPEC_F16CVTINT4FP4_ITER): Ditto.
(UNSPEC_F16CVTBIASINT4FP4_ITER): Ditto.
(f16cvtint4fp4): Ditto.
(avx10_3_vcvt2bf162<f16cvtint4fp4>s<mode>): Ditto.
(avx10_3_vcvtbf162<f16cvtint4fp4>s<mode>): Ditto.
(avx10_3_vcvtbias<f16cvtint4fp4>s<mode>): Ditto.
* config/i386/avx10_3int4fp4intrin.h: New file.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp
(check_effective_target_avx10_3): New.
* gcc.target/i386/avx10_3-int4fp4-1.c: New test.
* gcc.target/i386/avx10_3-vcvt2bf162bf4s-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvt2bf162bf4s-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvt2bf162sns-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvt2bf162sns-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvt2bf162uns-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvt2bf162uns-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvt2ph2sns-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvt2ph2sns-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvt2ph2uns-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvt2ph2uns-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvtbf162bf4s-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvtbf162bf4s-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvtbf162sns-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvtbf162sns-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvtbf162uns-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvtbf162uns-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvtbiasbf162bf4s-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvtbiasbf162bf4s-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvtbiasph2bf4s-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvtbiasph2bf4s-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvtph2bf4s-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvtph2bf4s-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvtph2sns-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvtph2sns-2.h: Ditto.
* gcc.target/i386/avx10_3-vcvtph2uns-2.c: Ditto.
* gcc.target/i386/avx10_3-vcvtph2uns-2.h: Ditto.
* gcc.target/i386/int4-fp4-helper.h: New helper function.
---
gcc/config.gcc | 3 +-
gcc/config/i386/avx10_3int4fp4intrin.h | 360 ++++++++++++++++++
gcc/config/i386/i386-builtin-types.def | 19 +
gcc/config/i386/i386-builtin.def | 44 +++
gcc/config/i386/i386-expand.cc | 17 +
gcc/config/i386/immintrin.h | 2 +
gcc/config/i386/sse.md | 90 ++++-
.../gcc.target/i386/avx10_3-int4fp4-1.c | 119 ++++++
.../i386/avx10_3-vcvt2bf162bf4s-2.c | 20 +
.../i386/avx10_3-vcvt2bf162bf4s-2.h | 53 +++
.../gcc.target/i386/avx10_3-vcvt2bf162sns-2.c | 20 +
.../gcc.target/i386/avx10_3-vcvt2bf162sns-2.h | 53 +++
.../gcc.target/i386/avx10_3-vcvt2bf162uns-2.c | 20 +
.../gcc.target/i386/avx10_3-vcvt2bf162uns-2.h | 51 +++
.../gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.c | 20 +
.../gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.h | 53 +++
.../gcc.target/i386/avx10_3-vcvt2ph2sns-2.c | 20 +
.../gcc.target/i386/avx10_3-vcvt2ph2sns-2.h | 53 +++
.../gcc.target/i386/avx10_3-vcvt2ph2uns-2.c | 20 +
.../gcc.target/i386/avx10_3-vcvt2ph2uns-2.h | 51 +++
.../gcc.target/i386/avx10_3-vcvtbf162bf4s-2.c | 18 +
.../gcc.target/i386/avx10_3-vcvtbf162bf4s-2.h | 46 +++
.../gcc.target/i386/avx10_3-vcvtbf162sns-2.c | 18 +
.../gcc.target/i386/avx10_3-vcvtbf162sns-2.h | 46 +++
.../gcc.target/i386/avx10_3-vcvtbf162uns-2.c | 18 +
.../gcc.target/i386/avx10_3-vcvtbf162uns-2.h | 42 ++
.../i386/avx10_3-vcvtbiasbf162bf4s-2.c | 18 +
.../i386/avx10_3-vcvtbiasbf162bf4s-2.h | 49 +++
.../i386/avx10_3-vcvtbiasph2bf4s-2.c | 18 +
.../i386/avx10_3-vcvtbiasph2bf4s-2.h | 49 +++
.../gcc.target/i386/avx10_3-vcvtph2bf4s-2.c | 18 +
.../gcc.target/i386/avx10_3-vcvtph2bf4s-2.h | 46 +++
.../gcc.target/i386/avx10_3-vcvtph2sns-2.c | 18 +
.../gcc.target/i386/avx10_3-vcvtph2sns-2.h | 46 +++
.../gcc.target/i386/avx10_3-vcvtph2uns-2.c | 18 +
.../gcc.target/i386/avx10_3-vcvtph2uns-2.h | 42 ++
.../gcc.target/i386/int4-fp4-helper.h | 226 +++++++++++
gcc/testsuite/lib/target-supports.exp | 15 +
38 files changed, 1836 insertions(+), 3 deletions(-)
create mode 100644 gcc/config/i386/avx10_3int4fp4intrin.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-int4fp4-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162bf4s-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162bf4s-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162sns-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162sns-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162uns-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162uns-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2sns-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2sns-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2uns-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2uns-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162bf4s-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162bf4s-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162sns-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162sns-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162uns-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162uns-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasbf162bf4s-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasbf162bf4s-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasph2bf4s-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasph2bf4s-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2bf4s-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2bf4s-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2sns-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2sns-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2uns-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2uns-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/int4-fp4-helper.h
diff --git a/gcc/config.gcc b/gcc/config.gcc
index d5fdbd0b864..dad0e71bab0 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -489,7 +489,8 @@ i[34567]86-*-* | x86_64-*-*)
avx10_2minmaxintrin.h avx10_2copyintrin.h
amxavx512intrin.h amxfp8intrin.h movrsintrin.h
amxmovrsintrin.h avx512bmmintrin.h avx512bmmvlintrin.h
- avx10v2auxintrin.h avx10v1auxintrin.h acev1intrin.h"
+ avx10v2auxintrin.h avx10v1auxintrin.h acev1intrin.h
+ avx10_3int4fp4intrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/avx10_3int4fp4intrin.h
b/gcc/config/i386/avx10_3int4fp4intrin.h
new file mode 100644
index 00000000000..699a8bb34f1
--- /dev/null
+++ b/gcc/config/i386/avx10_3int4fp4intrin.h
@@ -0,0 +1,360 @@
+/* Copyright (C) 2026 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+#error "Never use <avx10_3int4fp4intrin.h> directly; include <immintrin.h>
instead."
+#endif
+
+#ifndef _AVX10_3INT4FP4INTRIN_H_INCLUDED
+#define _AVX10_3INT4FP4INTRIN_H_INCLUDED
+
+#if !defined(__AVX10_3__)
+#pragma GCC push_options
+#pragma GCC target("avx10.3")
+#define __DISABLE_AVX10_3__
+#endif /* __AVX10_3__ */
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_2bf16_bf4 (__m128bh __A, __m128bh __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2bf162bf4s128 ((__v8bf) __A,
+ (__v8bf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_2bf16_bf4 (__m256bh __A, __m256bh __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2bf162bf4s256 ((__v16bf) __A,
+ (__v16bf) __B);
+}
+
+extern __inline__ __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_2bf16_bf4 (__m512bh __A, __m512bh __B)
+{
+ return (__m256i) __builtin_ia32_vcvt2bf162bf4s512 ((__v32bf) __A,
+ (__v32bf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_bf16_bf4 (__m128bh __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf162bf4s128 ((__v8bf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_bf16_bf4 (__m256bh __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf162bf4s256 ((__v16bf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_bf16_bf4 (__m512bh __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf162bf4s512 ((__v32bf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_2ph_bf4 (__m128h __A, __m128h __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2ph2bf4s128 ((__v8hf) __A,
+ (__v8hf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_2ph_bf4 (__m256h __A, __m256h __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2ph2bf4s256 ((__v16hf) __A,
+ (__v16hf) __B);
+}
+
+extern __inline__ __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_2ph_bf4 (__m512h __A, __m512h __B)
+{
+ return (__m256i) __builtin_ia32_vcvt2ph2bf4s512 ((__v32hf) __A,
+ (__v32hf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_ph_bf4 (__m128h __A)
+{
+ return (__m128i) __builtin_ia32_vcvtph2bf4s128 ((__v8hf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_ph_bf4 (__m256h __A)
+{
+ return (__m128i) __builtin_ia32_vcvtph2bf4s256 ((__v16hf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_ph_bf4 (__m512h __A)
+{
+ return (__m128i) __builtin_ia32_vcvtph2bf4s512 ((__v32hf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_2bf16_epi4 (__m128bh __A, __m128bh __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2bf162sns128 ((__v8bf) __A,
+ (__v8bf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_2bf16_epi4 (__m256bh __A, __m256bh __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2bf162sns256 ((__v16bf) __A,
+ (__v16bf) __B);
+}
+
+extern __inline__ __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_2bf16_epi4 (__m512bh __A, __m512bh __B)
+{
+ return (__m256i) __builtin_ia32_vcvt2bf162sns512 ((__v32bf) __A,
+ (__v32bf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_bf16_epi4 (__m128bh __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf162sns128 ((__v8bf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_bf16_epi4 (__m256bh __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf162sns256 ((__v16bf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_bf16_epi4 (__m512bh __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf162sns512 ((__v32bf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_2bf16_epu4 (__m128bh __A, __m128bh __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2bf162uns128 ((__v8bf) __A,
+ (__v8bf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_2bf16_epu4 (__m256bh __A, __m256bh __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2bf162uns256 ((__v16bf) __A,
+ (__v16bf) __B);
+}
+
+extern __inline__ __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_2bf16_epu4 (__m512bh __A, __m512bh __B)
+{
+ return (__m256i) __builtin_ia32_vcvt2bf162uns512 ((__v32bf) __A,
+ (__v32bf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_bf16_epu4 (__m128bh __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf162uns128 ((__v8bf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_bf16_epu4 (__m256bh __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf162uns256 ((__v16bf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_bf16_epu4 (__m512bh __A)
+{
+ return (__m128i) __builtin_ia32_vcvtbf162uns512 ((__v32bf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_2ph_epi4 (__m128h __A, __m128h __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2ph2sns128 ((__v8hf) __A,
+ (__v8hf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_2ph_epi4 (__m256h __A, __m256h __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2ph2sns256 ((__v16hf) __A,
+ (__v16hf) __B);
+}
+
+extern __inline__ __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_2ph_epi4 (__m512h __A, __m512h __B)
+{
+ return (__m256i) __builtin_ia32_vcvt2ph2sns512 ((__v32hf) __A,
+ (__v32hf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_ph_epi4 (__m128h __A)
+{
+ return (__m128i) __builtin_ia32_vcvtph2sns128 ((__v8hf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_ph_epi4 (__m256h __A)
+{
+ return (__m128i) __builtin_ia32_vcvtph2sns256 ((__v16hf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_ph_epi4 (__m512h __A)
+{
+ return (__m128i) __builtin_ia32_vcvtph2sns512 ((__v32hf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_2ph_epu4 (__m128h __A, __m128h __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2ph2uns128 ((__v8hf) __A,
+ (__v8hf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_2ph_epu4 (__m256h __A, __m256h __B)
+{
+ return (__m128i) __builtin_ia32_vcvt2ph2uns256 ((__v16hf) __A,
+ (__v16hf) __B);
+}
+
+extern __inline__ __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_2ph_epu4 (__m512h __A, __m512h __B)
+{
+ return (__m256i) __builtin_ia32_vcvt2ph2uns512 ((__v32hf) __A,
+ (__v32hf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_ph_epu4 (__m128h __A)
+{
+ return (__m128i) __builtin_ia32_vcvtph2uns128 ((__v8hf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_ph_epu4 (__m256h __A)
+{
+ return (__m128i) __builtin_ia32_vcvtph2uns256 ((__v16hf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_ph_epu4 (__m512h __A)
+{
+ return (__m128i) __builtin_ia32_vcvtph2uns512 ((__v32hf) __A);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_biasbf16_bf4 (__m128i __A, __m128bh __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasbf162bf4s128 ((__v16qi) __A,
+ (__v8bf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_biasbf16_bf4 (__m256i __A, __m256bh __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasbf162bf4s256 ((__v32qi) __A,
+ (__v16bf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_biasbf16_bf4 (__m512i __A, __m512bh __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasbf162bf4s512 ((__v64qi) __A,
+ (__v32bf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_cvts_biasph_bf4 (__m128i __A, __m128h __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasph2bf4s128 ((__v16qi) __A,
+ (__v8hf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_cvts_biasph_bf4 (__m256i __A, __m256h __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasph2bf4s256 ((__v32qi) __A,
+ (__v16hf) __B);
+}
+
+extern __inline__ __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_cvts_biasph_bf4 (__m512i __A, __m512h __B)
+{
+ return (__m128i) __builtin_ia32_vcvtbiasph2bf4s512 ((__v64qi) __A,
+ (__v32hf) __B);
+}
+
+#ifdef __DISABLE_AVX10_3__
+#undef __DISABLE_AVX10_3__
+#pragma GCC pop_options
+#endif /* __DISABLE_AVX10_3__ */
+
+#endif /* __AVX10_3INT4FP4INTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/i386-builtin-types.def
b/gcc/config/i386/i386-builtin-types.def
index 30a978770eb..ebdc2638633 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1513,3 +1513,22 @@ DEF_FUNCTION_TYPE (VOID, UQI, V16SI, SI)
DEF_FUNCTION_TYPE (VOID, UQI, V32BF, V32BF)
DEF_FUNCTION_TYPE (VOID, UQI, V64QI, V64QI)
DEF_FUNCTION_TYPE (VOID, UQI, V64QI, V64QI, SI)
+
+# AVX10_3 builtins
+DEF_FUNCTION_TYPE (V16QI, V8BF, V8BF)
+DEF_FUNCTION_TYPE (V16QI, V16BF, V16BF)
+DEF_FUNCTION_TYPE (V32QI, V32BF, V32BF)
+DEF_FUNCTION_TYPE (V16QI, V8HF, V8HF)
+DEF_FUNCTION_TYPE (V16QI, V16HF, V16HF)
+DEF_FUNCTION_TYPE (V32QI, V32HF, V32HF)
+DEF_FUNCTION_TYPE (V16QI, V8BF)
+DEF_FUNCTION_TYPE (V16QI, V16BF)
+DEF_FUNCTION_TYPE (V16QI, V32BF)
+DEF_FUNCTION_TYPE (V16QI, V8HF)
+DEF_FUNCTION_TYPE (V16QI, V16HF)
+DEF_FUNCTION_TYPE (V16QI, V32HF)
+DEF_FUNCTION_TYPE (V16QI, V16QI, V8BF)
+DEF_FUNCTION_TYPE (V16QI, V32QI, V16BF)
+DEF_FUNCTION_TYPE (V16QI, V64QI, V32BF)
+DEF_FUNCTION_TYPE (V16QI, V32QI, V16HF)
+DEF_FUNCTION_TYPE (V16QI, V64QI, V32HF)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 6afae026040..df19551d352 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3439,6 +3439,50 @@ BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
CODE_FOR_avx10v2aux_sym_truncatev4siv4qi2
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
CODE_FOR_avx10v2aux_sym_truncatev8siv8qi2_mask,
"__builtin_ia32_vpmovssdb256_mask", IX86_BUILTIN_VPMOVSSDB256_MASK, UNKNOWN,
(int) V16QI_FTYPE_V8SI_V16QI_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10V2AUX,
CODE_FOR_avx10v2aux_sym_truncatev16siv16qi2_mask,
"__builtin_ia32_vpmovssdb512_mask", IX86_BUILTIN_VPMOVSSDB512_MASK, UNKNOWN,
(int) V16QI_FTYPE_V16SI_V16QI_UHI)
+/* AVX10.3. */
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2bf162bf4sv8bf,
"__builtin_ia32_vcvt2bf162bf4s128", IX86_BUILTIN_CVT2BF162BF4S128, UNKNOWN,
(int) V16QI_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2bf162bf4sv16bf,
"__builtin_ia32_vcvt2bf162bf4s256", IX86_BUILTIN_CVT2BF162BF4S256, UNKNOWN,
(int) V16QI_FTYPE_V16BF_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2bf162bf4sv32bf,
"__builtin_ia32_vcvt2bf162bf4s512", IX86_BUILTIN_CVT2BF162BF4S512, UNKNOWN,
(int) V32QI_FTYPE_V32BF_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbf162bf4sv8bf,
"__builtin_ia32_vcvtbf162bf4s128", IX86_BUILTIN_CVTBF162BF4S128, UNKNOWN, (int)
V16QI_FTYPE_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbf162bf4sv16bf,
"__builtin_ia32_vcvtbf162bf4s256", IX86_BUILTIN_CVTBF162BF4S256, UNKNOWN, (int)
V16QI_FTYPE_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbf162bf4sv32bf,
"__builtin_ia32_vcvtbf162bf4s512", IX86_BUILTIN_CVTBF162BF4S512, UNKNOWN, (int)
V16QI_FTYPE_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2ph2bf4sv8hf,
"__builtin_ia32_vcvt2ph2bf4s128", IX86_BUILTIN_CVT2PH2BF4S128, UNKNOWN, (int)
V16QI_FTYPE_V8HF_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2ph2bf4sv16hf,
"__builtin_ia32_vcvt2ph2bf4s256", IX86_BUILTIN_CVT2PH2BF4S256, UNKNOWN, (int)
V16QI_FTYPE_V16HF_V16HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2ph2bf4sv32hf,
"__builtin_ia32_vcvt2ph2bf4s512", IX86_BUILTIN_CVT2PH2BF4S512, UNKNOWN, (int)
V32QI_FTYPE_V32HF_V32HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtph2bf4sv8hf,
"__builtin_ia32_vcvtph2bf4s128", IX86_BUILTIN_CVTPH2BF4S128, UNKNOWN, (int)
V16QI_FTYPE_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtph2bf4sv16hf,
"__builtin_ia32_vcvtph2bf4s256", IX86_BUILTIN_CVTPH2BF4S256, UNKNOWN, (int)
V16QI_FTYPE_V16HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtph2bf4sv32hf,
"__builtin_ia32_vcvtph2bf4s512", IX86_BUILTIN_CVTPH2BF4S512, UNKNOWN, (int)
V16QI_FTYPE_V32HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2bf162snsv8bf,
"__builtin_ia32_vcvt2bf162sns128", IX86_BUILTIN_CVT2BF162SNS128, UNKNOWN, (int)
V16QI_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2bf162snsv16bf,
"__builtin_ia32_vcvt2bf162sns256", IX86_BUILTIN_CVT2BF162SNS256, UNKNOWN, (int)
V16QI_FTYPE_V16BF_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2bf162snsv32bf,
"__builtin_ia32_vcvt2bf162sns512", IX86_BUILTIN_CVT2BF162SNS512, UNKNOWN, (int)
V32QI_FTYPE_V32BF_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbf162snsv8bf,
"__builtin_ia32_vcvtbf162sns128", IX86_BUILTIN_CVTBF162SNS128, UNKNOWN, (int)
V16QI_FTYPE_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbf162snsv16bf,
"__builtin_ia32_vcvtbf162sns256", IX86_BUILTIN_CVTBF162SNS256, UNKNOWN, (int)
V16QI_FTYPE_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbf162snsv32bf,
"__builtin_ia32_vcvtbf162sns512", IX86_BUILTIN_CVTBF162SNS512, UNKNOWN, (int)
V16QI_FTYPE_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2bf162unsv8bf,
"__builtin_ia32_vcvt2bf162uns128", IX86_BUILTIN_CVT2BF162UNS128, UNKNOWN, (int)
V16QI_FTYPE_V8BF_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2bf162unsv16bf,
"__builtin_ia32_vcvt2bf162uns256", IX86_BUILTIN_CVT2BF162UNS256, UNKNOWN, (int)
V16QI_FTYPE_V16BF_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2bf162unsv32bf,
"__builtin_ia32_vcvt2bf162uns512", IX86_BUILTIN_CVT2BF162UNS512, UNKNOWN, (int)
V32QI_FTYPE_V32BF_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbf162unsv8bf,
"__builtin_ia32_vcvtbf162uns128", IX86_BUILTIN_CVTBF162UNS128, UNKNOWN, (int)
V16QI_FTYPE_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbf162unsv16bf,
"__builtin_ia32_vcvtbf162uns256", IX86_BUILTIN_CVTBF162UNS256, UNKNOWN, (int)
V16QI_FTYPE_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbf162unsv32bf,
"__builtin_ia32_vcvtbf162uns512", IX86_BUILTIN_CVTBF162UNS512, UNKNOWN, (int)
V16QI_FTYPE_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2ph2snsv8hf,
"__builtin_ia32_vcvt2ph2sns128", IX86_BUILTIN_CVT2PH2SNS128, UNKNOWN, (int)
V16QI_FTYPE_V8HF_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2ph2snsv16hf,
"__builtin_ia32_vcvt2ph2sns256", IX86_BUILTIN_CVT2PH2SNS256, UNKNOWN, (int)
V16QI_FTYPE_V16HF_V16HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2ph2snsv32hf,
"__builtin_ia32_vcvt2ph2sns512", IX86_BUILTIN_CVT2PH2SNS512, UNKNOWN, (int)
V32QI_FTYPE_V32HF_V32HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtph2snsv8hf,
"__builtin_ia32_vcvtph2sns128", IX86_BUILTIN_CVTPH2SNS128, UNKNOWN, (int)
V16QI_FTYPE_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtph2snsv16hf,
"__builtin_ia32_vcvtph2sns256", IX86_BUILTIN_CVTPH2SNS256, UNKNOWN, (int)
V16QI_FTYPE_V16HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtph2snsv32hf,
"__builtin_ia32_vcvtph2sns512", IX86_BUILTIN_CVTPH2SNS512, UNKNOWN, (int)
V16QI_FTYPE_V32HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2ph2unsv8hf,
"__builtin_ia32_vcvt2ph2uns128", IX86_BUILTIN_CVT2PH2UNS128, UNKNOWN, (int)
V16QI_FTYPE_V8HF_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2ph2unsv16hf,
"__builtin_ia32_vcvt2ph2uns256", IX86_BUILTIN_CVT2PH2UNS256, UNKNOWN, (int)
V16QI_FTYPE_V16HF_V16HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvt2ph2unsv32hf,
"__builtin_ia32_vcvt2ph2uns512", IX86_BUILTIN_CVT2PH2UNS512, UNKNOWN, (int)
V32QI_FTYPE_V32HF_V32HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtph2unsv8hf,
"__builtin_ia32_vcvtph2uns128", IX86_BUILTIN_CVTPH2UNS128, UNKNOWN, (int)
V16QI_FTYPE_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtph2unsv16hf,
"__builtin_ia32_vcvtph2uns256", IX86_BUILTIN_CVTPH2UNS256, UNKNOWN, (int)
V16QI_FTYPE_V16HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtph2unsv32hf,
"__builtin_ia32_vcvtph2uns512", IX86_BUILTIN_CVTPH2UNS512, UNKNOWN, (int)
V16QI_FTYPE_V32HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbiasbf162bf4sv8bf,
"__builtin_ia32_vcvtbiasbf162bf4s128", IX86_BUILTIN_CVTBIASBF162BF4S128,
UNKNOWN, (int) V16QI_FTYPE_V16QI_V8BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbiasbf162bf4sv16bf,
"__builtin_ia32_vcvtbiasbf162bf4s256", IX86_BUILTIN_CVTBIASBF162BF4S256,
UNKNOWN, (int) V16QI_FTYPE_V32QI_V16BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbiasbf162bf4sv32bf,
"__builtin_ia32_vcvtbiasbf162bf4s512", IX86_BUILTIN_CVTBIASBF162BF4S512,
UNKNOWN, (int) V16QI_FTYPE_V64QI_V32BF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbiasph2bf4sv8hf,
"__builtin_ia32_vcvtbiasph2bf4s128", IX86_BUILTIN_CVTBIASPH2BF4S128, UNKNOWN,
(int) V16QI_FTYPE_V16QI_V8HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbiasph2bf4sv16hf,
"__builtin_ia32_vcvtbiasph2bf4s256", IX86_BUILTIN_CVTBIASPH2BF4S256, UNKNOWN,
(int) V16QI_FTYPE_V32QI_V16HF)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_avx10_3_vcvtbiasph2bf4sv32hf,
"__builtin_ia32_vcvtbiasph2bf4s512", IX86_BUILTIN_CVTBIASPH2BF4S512, UNKNOWN,
(int) V16QI_FTYPE_V64QI_V32HF)
+
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index c02e7128b9d..5ee4bbec237 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -12739,6 +12739,12 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V8BF_FTYPE_V4SF:
case V16QI_FTYPE_V32QI:
case V32QI_FTYPE_V64QI:
+ case V16QI_FTYPE_V8BF:
+ case V16QI_FTYPE_V16BF:
+ case V16QI_FTYPE_V32BF:
+ case V16QI_FTYPE_V8HF:
+ case V16QI_FTYPE_V16HF:
+ case V16QI_FTYPE_V32HF:
nargs = 1;
break;
case V4SF_FTYPE_V4SF_VEC_MERGE:
@@ -12808,6 +12814,12 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V4DI_FTYPE_V8SI_V8SI:
case V4DI_FTYPE_V32QI_V32QI:
case V8DI_FTYPE_V64QI_V64QI:
+ case V16QI_FTYPE_V8BF_V8BF:
+ case V16QI_FTYPE_V16BF_V16BF:
+ case V32QI_FTYPE_V32BF_V32BF:
+ case V16QI_FTYPE_V8HF_V8HF:
+ case V16QI_FTYPE_V16HF_V16HF:
+ case V32QI_FTYPE_V32HF_V32HF:
if (comparison == UNKNOWN)
return ix86_expand_binop_builtin (icode, exp, target);
nargs = 2;
@@ -12877,7 +12889,12 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V16BF_FTYPE_V16SF_UHI:
case V8BF_FTYPE_V8SF_UQI:
case V8BF_FTYPE_V4SF_UQI:
+ case V16QI_FTYPE_V16QI_V8BF:
+ case V16QI_FTYPE_V32QI_V16BF:
+ case V16QI_FTYPE_V64QI_V32BF:
case V16QI_FTYPE_V16QI_V8HF:
+ case V16QI_FTYPE_V32QI_V16HF:
+ case V16QI_FTYPE_V64QI_V32HF:
nargs = 2;
break;
case V2DI_FTYPE_V2DI_INT_CONVERT:
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 74063ee4053..20578e92a99 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -168,4 +168,6 @@
#include <acev1intrin.h>
+#include <avx10_3int4fp4intrin.h>
+
#endif /* _IMMINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 3a445c9746d..a60722c785f 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -289,6 +289,22 @@
UNSPEC_TCVTROWPS2FP16H
UNSPEC_TCVTROWPS2FP16L
UNSPEC_TILEMOVROWEXTRACT
+
+ ;; For AVX10_3 support
+ UNSPEC_VCVT2BF162BF4S
+ UNSPEC_VCVT2BF162SNS
+ UNSPEC_VCVT2BF162UNS
+ UNSPEC_VCVTBF162BF4S
+ UNSPEC_VCVTBF162SNS
+ UNSPEC_VCVTBF162UNS
+ UNSPEC_VCVT2PH2BF4S
+ UNSPEC_VCVT2PH2SNS
+ UNSPEC_VCVT2PH2UNS
+ UNSPEC_VCVTPH2BF4S
+ UNSPEC_VCVTPH2SNS
+ UNSPEC_VCVTPH2UNS
+ UNSPEC_VCVTBIASBF162BF4S
+ UNSPEC_VCVTBIASPH2BF4S
])
(define_c_enum "unspecv" [
@@ -33186,7 +33202,8 @@
"vcvt2ps2phx\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>,
%1, %2<round_mask_op3>}")
(define_mode_attr ssebvecmode
- [(V8HF "V16QI") (V16HF "V32QI") (V32HF "V64QI")])
+ [(V8HF "V16QI") (V16HF "V32QI") (V32HF "V64QI")
+ (V8BF "V16QI") (V16BF "V32QI") (V32BF "V64QI")])
(define_int_iterator UNSPEC_CONVERTFP8_PACK
[UNSPEC_VCVT2PH2BF8 UNSPEC_VCVT2PH2BF8S
@@ -33210,7 +33227,8 @@
(define_mode_attr ssebvecmode_2
[(V8HF "V16QI") (V16HF "V16QI") (V32HF "V32QI")
- (V16QI "V16QI") (V32QI "V16QI") (V64QI "V32QI")])
+ (V16QI "V16QI") (V32QI "V16QI") (V64QI "V32QI")
+ (V8BF "V16QI") (V16BF "V16QI") (V32BF "V32QI")])
(define_mode_attr iptrssebvec_2
[(V8HF "q") (V16HF "") (V32HF "")])
@@ -34996,3 +35014,71 @@
"TARGET_ACEV1"
"top4mxbssps\t{%3, %2, %1, %%tmm%c0|tmm%c0, %1, %2, %3}"
[(set_attr "prefix" "evex")])
+
+(define_int_iterator UNSPEC_2F16CVTINT4FP4_ITER
+ [UNSPEC_VCVT2BF162BF4S
+ UNSPEC_VCVT2BF162SNS
+ UNSPEC_VCVT2BF162UNS
+ UNSPEC_VCVT2PH2BF4S
+ UNSPEC_VCVT2PH2SNS
+ UNSPEC_VCVT2PH2UNS])
+
+(define_int_iterator UNSPEC_F16CVTINT4FP4_ITER
+ [UNSPEC_VCVTBF162BF4S
+ UNSPEC_VCVTBF162SNS
+ UNSPEC_VCVTBF162UNS
+ UNSPEC_VCVTPH2BF4S
+ UNSPEC_VCVTPH2SNS
+ UNSPEC_VCVTPH2UNS])
+
+(define_int_iterator UNSPEC_F16CVTBIASINT4FP4_ITER
+ [UNSPEC_VCVTBIASBF162BF4S
+ UNSPEC_VCVTBIASPH2BF4S])
+
+(define_int_attr f16cvtint4fp4
+ [(UNSPEC_VCVT2BF162BF4S "bf162bf4")
+ (UNSPEC_VCVT2BF162SNS "bf162sn")
+ (UNSPEC_VCVT2BF162UNS "bf162un")
+ (UNSPEC_VCVTBF162BF4S "bf162bf4")
+ (UNSPEC_VCVTBF162SNS "bf162sn")
+ (UNSPEC_VCVTBF162UNS "bf162un")
+ (UNSPEC_VCVTBIASBF162BF4S "bf162bf4")
+ (UNSPEC_VCVT2PH2BF4S "ph2bf4")
+ (UNSPEC_VCVT2PH2SNS "ph2sn")
+ (UNSPEC_VCVT2PH2UNS "ph2un")
+ (UNSPEC_VCVTPH2BF4S "ph2bf4")
+ (UNSPEC_VCVTPH2SNS "ph2sn")
+ (UNSPEC_VCVTPH2UNS "ph2un")
+ (UNSPEC_VCVTBIASPH2BF4S "ph2bf4")])
+
+(define_insn "avx10_3_vcvt2<f16cvtint4fp4>s<mode>"
+ [(set (match_operand:<ssebvecmode_2> 0 "register_operand" "=v")
+ (unspec:<ssebvecmode_2>
+ [(match_operand:VHFBF 1 "register_operand" "v")
+ (match_operand:VHFBF 2 "nonimmediate_operand" "vm")]
+ UNSPEC_2F16CVTINT4FP4_ITER))]
+ "TARGET_AVX10_3"
+ "vcvt2<f16cvtint4fp4>s\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "avx10_3_vcvt<f16cvtint4fp4>s<mode>"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (unspec:V16QI
+ [(match_operand:VHFBF 1 "nonimmediate_operand" "vm")]
+ UNSPEC_F16CVTINT4FP4_ITER))]
+ "TARGET_AVX10_3"
+ "vcvt<f16cvtint4fp4>s<vecmemsuffix>\t{%1, %0|%0, %1}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "avx10_3_vcvtbias<f16cvtint4fp4>s<mode>"
+ [(set (match_operand:V16QI 0 "register_operand" "=v")
+ (unspec:V16QI
+ [(match_operand:<ssebvecmode> 1 "register_operand" "v")
+ (match_operand:VHFBF 2 "nonimmediate_operand" "vm")]
+ UNSPEC_F16CVTBIASINT4FP4_ITER))]
+ "TARGET_AVX10_3"
+ "vcvtbias<f16cvtint4fp4>s\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-int4fp4-1.c
b/gcc/testsuite/gcc.target/i386/avx10_3-int4fp4-1.c
new file mode 100644
index 00000000000..a52a57ce062
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-int4fp4-1.c
@@ -0,0 +1,119 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10.3 -fno-fuse-ops-with-volatile-access -O2" } */
+/* { dg-final { scan-assembler-times "vcvt2bf162bf4s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2bf162bf4s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2bf162bf4s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf162bf4sx\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf162bf4sy\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf162bf4sz\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf4s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf4s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2bf4s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2bf4sx\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2bf4sy\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2bf4sz\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2bf162sns\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2bf162sns\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2bf162sns\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf162snsx\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf162snsy\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf162snsz\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2bf162uns\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2bf162uns\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2bf162uns\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf162unsx\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf162unsy\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbf162unsz\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2sns\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2sns\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2sns\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2snsx\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2snsy\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2snsz\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2uns\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2uns\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvt2ph2uns\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2unsx\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2unsy\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtph2unsz\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasbf162bf4s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasbf162bf4s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasbf162bf4s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf4s\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf4s\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtbiasph2bf4s\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128bh x1, x2;
+volatile __m256bh y, y2;
+volatile __m512bh z1, z2;
+volatile __m128h xh1, xh2;
+volatile __m256h yh1, yh2;
+volatile __m512h zh1, zh2;
+volatile __m128i x3, x4, x5;
+volatile __m256i y3, y4, y5;
+volatile __m512i z3, z4, z5;
+volatile __mmask16 m16;
+volatile __mmask32 m32;
+volatile __mmask64 m64;
+
+void extern
+avx10_3_int4fp4_test (void)
+{
+ x3 = _mm_cvts_2bf16_bf4 (x1, x2);
+ x3 = _mm256_cvts_2bf16_bf4 (y, y2);
+ y3 = _mm512_cvts_2bf16_bf4 (z1, z2);
+
+ x3 = _mm_cvts_bf16_bf4 (x1);
+ x3 = _mm256_cvts_bf16_bf4 (y);
+ x3 = _mm512_cvts_bf16_bf4 (z1);
+
+ x3 = _mm_cvts_2ph_bf4 (xh1, xh2);
+ x3 = _mm256_cvts_2ph_bf4 (yh1, yh2);
+ y3 = _mm512_cvts_2ph_bf4 (zh1, zh2);
+
+ x3 = _mm_cvts_ph_bf4 (xh1);
+ x3 = _mm256_cvts_ph_bf4 (yh1);
+ x3 = _mm512_cvts_ph_bf4 (zh1);
+
+ x3 = _mm_cvts_2bf16_epi4 (x1, x2);
+ x3 = _mm256_cvts_2bf16_epi4 (y, y2);
+ y3 = _mm512_cvts_2bf16_epi4 (z1, z2);
+
+ x3 = _mm_cvts_bf16_epi4 (x1);
+ x3 = _mm256_cvts_bf16_epi4 (y);
+ x3 = _mm512_cvts_bf16_epi4 (z1);
+
+ x3 = _mm_cvts_2bf16_epu4 (x1, x2);
+ x3 = _mm256_cvts_2bf16_epu4 (y, y2);
+ y3 = _mm512_cvts_2bf16_epu4 (z1, z2);
+
+ x3 = _mm_cvts_bf16_epu4 (x1);
+ x3 = _mm256_cvts_bf16_epu4 (y);
+ x3 = _mm512_cvts_bf16_epu4 (z1);
+
+ x3 = _mm_cvts_2ph_epi4 (xh1, xh2);
+ x3 = _mm256_cvts_2ph_epi4 (yh1, yh2);
+ y3 = _mm512_cvts_2ph_epi4 (zh1, zh2);
+
+ x3 = _mm_cvts_ph_epi4 (xh1);
+ x3 = _mm256_cvts_ph_epi4 (yh1);
+ x3 = _mm512_cvts_ph_epi4 (zh1);
+
+ x3 = _mm_cvts_2ph_epu4 (xh1, xh2);
+ x3 = _mm256_cvts_2ph_epu4 (yh1, yh2);
+ y3 = _mm512_cvts_2ph_epu4 (zh1, zh2);
+
+ x3 = _mm_cvts_ph_epu4 (xh1);
+ x3 = _mm256_cvts_ph_epu4 (yh1);
+ x3 = _mm512_cvts_ph_epu4 (zh1);
+
+ x3 = _mm_cvts_biasbf16_bf4 (x4, x2);
+ x3 = _mm256_cvts_biasbf16_bf4 (y4, y2);
+ x3 = _mm512_cvts_biasbf16_bf4 (z4, z2);
+
+ x3 = _mm_cvts_biasph_bf4 (x4, xh2);
+ x3 = _mm256_cvts_biasph_bf4 (y4, yh2);
+ x3 = _mm512_cvts_biasph_bf4 (z4, zh2);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162bf4s-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162bf4s-2.c
new file mode 100644
index 00000000000..b773c3dcff3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162bf4s-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#include "avx10_3-vcvt2bf162bf4s-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2bf162bf4s-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2bf162bf4s-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162bf4s-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162bf4s-2.h
new file mode 100644
index 00000000000..645e1504e96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162bf4s-2.h
@@ -0,0 +1,53 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_HALF / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, __bf16 *s1, __bf16 *s2)
+{
+ int i;
+ unsigned low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_bf16_to_bf4 (s2[i * 2]);
+ high = convert_bf16_to_bf4 (s2[i * 2 + 1]);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ else if (i < SIZE)
+ {
+ low = convert_bf16_to_bf4 (s1[(i - SIZE / 2) * 2]);
+ high = convert_bf16_to_bf4 (s1[(i - SIZE / 2) * 2 + 1]);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i,sign;
+ UNION_TYPE (AVX512F_LEN_HALF, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, bf16_bf) src1, src2;
+ unsigned char res_ref[SIZE_DST];
+
+ sign = 1;
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = (__bf16) (sign * (2.5 * (1 << (i % 3))));
+ src2.a[i] = (__bf16) (-sign * (0.5 * (1 << (i % 5))));
+ sign = -sign;
+ }
+
+ CALC(res_ref, src1.a, src2.a);
+
+ res.x = INTRINSIC (_cvts_2bf16_bf4) (src1.x, src2.x);
+ if (UNION_CHECK (AVX512F_LEN_HALF, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162sns-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162sns-2.c
new file mode 100644
index 00000000000..f4135a660f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162sns-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#include "avx10_3-vcvt2bf162sns-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2bf162sns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2bf162sns-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162sns-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162sns-2.h
new file mode 100644
index 00000000000..3d19d74db95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162sns-2.h
@@ -0,0 +1,53 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_HALF / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, __bf16 *s1, __bf16 *s2)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_bf16_to_int4 (s2[i * 2], true);
+ high = convert_bf16_to_int4 (s2[i * 2 + 1], true);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ else if (i < SIZE)
+ {
+ low = convert_bf16_to_int4 (s1[(i - SIZE / 2) * 2], true);
+ high = convert_bf16_to_int4 (s1[(i - SIZE / 2) * 2 + 1], true);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i,sign;
+ UNION_TYPE (AVX512F_LEN_HALF, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, bf16_bf) src1, src2;
+ unsigned char res_ref[SIZE_DST];
+
+ sign = 1;
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = (__bf16) (sign * (2.5 * (1 << (i % 3))));
+ src2.a[i] = (__bf16) (-sign * (0.5 * (1 << (i % 5))));
+ sign = -sign;
+ }
+
+ CALC(res_ref, src1.a, src2.a);
+
+ res.x = INTRINSIC (_cvts_2bf16_epi4) (src1.x, src2.x);
+ if (UNION_CHECK (AVX512F_LEN_HALF, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162uns-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162uns-2.c
new file mode 100644
index 00000000000..15771cb2554
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162uns-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#include "avx10_3-vcvt2bf162uns-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2bf162uns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2bf162uns-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162uns-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162uns-2.h
new file mode 100644
index 00000000000..fbca4a683ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2bf162uns-2.h
@@ -0,0 +1,51 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_HALF / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, __bf16 *s1, __bf16 *s2)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_bf16_to_int4 (s2[i * 2], false);
+ high = convert_bf16_to_int4 (s2[i * 2 + 1], false);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ else if (i < SIZE)
+ {
+ low = convert_bf16_to_int4 (s1[(i - SIZE / 2) * 2], false);
+ high = convert_bf16_to_int4 (s1[(i - SIZE / 2) * 2 + 1], false);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN_HALF, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, bf16_bf) src1, src2;
+ unsigned char res_ref[SIZE_DST];
+
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = (__bf16) (2.5 * (1 << (i % 3)));
+ src2.a[i] = (__bf16) (0.5 * (1 << (i % 5)));
+ }
+
+ CALC(res_ref, src1.a, src2.a);
+
+ res.x = INTRINSIC (_cvts_2bf16_epu4) (src1.x, src2.x);
+ if (UNION_CHECK (AVX512F_LEN_HALF, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.c
new file mode 100644
index 00000000000..cc9dc15fd24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#include "avx10_3-vcvt2ph2bf4s-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2ph2bf4s-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2ph2bf4s-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.h
new file mode 100644
index 00000000000..2d6ffad9df4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2bf4s-2.h
@@ -0,0 +1,53 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_HALF / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, _Float16 *s1, _Float16 *s2)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_fp16_to_bf4 (s2[i * 2]);
+ high = convert_fp16_to_bf4 (s2[i * 2 + 1]);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ else if (i < SIZE)
+ {
+ low = convert_fp16_to_bf4 (s1[(i - SIZE / 2) * 2]);
+ high = convert_fp16_to_bf4 (s1[(i - SIZE / 2) * 2 + 1]);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i,sign;
+ UNION_TYPE (AVX512F_LEN_HALF, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, h) src1, src2;
+ unsigned char res_ref[SIZE_DST];
+
+ sign = 1;
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = (_Float16) (sign * (2.5 * (1 << (i % 3))));
+ src2.a[i] = (_Float16) (-sign * (0.5 * (1 << (i % 5))));
+ sign = -sign;
+ }
+
+ CALC(res_ref, src1.a, src2.a);
+
+ res.x = INTRINSIC (_cvts_2ph_bf4) (src1.x, src2.x);
+ if (UNION_CHECK (AVX512F_LEN_HALF, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2sns-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2sns-2.c
new file mode 100644
index 00000000000..fb96522ad8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2sns-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#include "avx10_3-vcvt2ph2sns-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2ph2sns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2ph2sns-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2sns-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2sns-2.h
new file mode 100644
index 00000000000..b86581862fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2sns-2.h
@@ -0,0 +1,53 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_HALF / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, _Float16 *s1, _Float16 *s2)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_fp16_to_int4 (s2[i * 2], true);
+ high = convert_fp16_to_int4 (s2[i * 2 + 1], true);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ else if (i < SIZE)
+ {
+ low = convert_fp16_to_int4 (s1[(i - SIZE / 2) * 2], true);
+ high = convert_fp16_to_int4 (s1[(i - SIZE / 2) * 2 + 1], true);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i,sign;
+ UNION_TYPE (AVX512F_LEN_HALF, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, h) src1, src2;
+ unsigned char res_ref[SIZE_DST];
+
+ sign = 1;
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = (_Float16) (sign * (2.5 * (1 << (i % 3))));
+ src2.a[i] = (_Float16) (-sign * (0.5 * (1 << (i % 5))));
+ sign = -sign;
+ }
+
+ CALC(res_ref, src1.a, src2.a);
+
+ res.x = INTRINSIC (_cvts_2ph_epi4) (src1.x, src2.x);
+ if (UNION_CHECK (AVX512F_LEN_HALF, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2uns-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2uns-2.c
new file mode 100644
index 00000000000..41c1c157e30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2uns-2.c
@@ -0,0 +1,20 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#include "avx10_3-vcvt2ph2uns-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2ph2uns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vcvt2ph2uns-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2uns-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2uns-2.h
new file mode 100644
index 00000000000..98043441f5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvt2ph2uns-2.h
@@ -0,0 +1,51 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_HALF / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, _Float16 *s1, _Float16 *s2)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_fp16_to_int4 (s2[i * 2], false);
+ high = convert_fp16_to_int4 (s2[i * 2 + 1], false);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ else if (i < SIZE)
+ {
+ low = convert_fp16_to_int4 (s1[(i - SIZE / 2) * 2], false);
+ high = convert_fp16_to_int4 (s1[(i - SIZE / 2) * 2 + 1], false);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN_HALF, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, h) src1, src2;
+ unsigned char res_ref[SIZE_DST];
+
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = (_Float16) (2.5 * (1 << (i % 3)));
+ src2.a[i] = (_Float16) (0.5 * (1 << (i % 5)));
+ }
+
+ CALC(res_ref, src1.a, src2.a);
+
+ res.x = INTRINSIC (_cvts_2ph_epu4) (src1.x, src2.x);
+ if (UNION_CHECK (AVX512F_LEN_HALF, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162bf4s-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162bf4s-2.c
new file mode 100644
index 00000000000..17b69279d89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162bf4s-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#define AVX512F_LEN_QUAR 128
+#include "avx10_3-vcvtbf162bf4s-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#include "avx10_3-vcvtbf162bf4s-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#include "avx10_3-vcvtbf162bf4s-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162bf4s-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162bf4s-2.h
new file mode 100644
index 00000000000..d7afc2f4e0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162bf4s-2.h
@@ -0,0 +1,46 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_QUAR / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, __bf16 *s)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_bf16_to_bf4 (s[i * 2]);
+ high = convert_bf16_to_bf4 (s[i * 2 + 1]);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i,sign;
+ UNION_TYPE (AVX512F_LEN_QUAR, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, bf16_bf) src;
+ unsigned char res_ref[SIZE_DST];
+
+ sign = 1;
+ for (i = 0; i < SIZE; i++)
+ {
+ src.a[i] = (__bf16) (sign * (2.5 * (1 << (i % 3))));
+ sign = -sign;
+ }
+
+ CALC(res_ref, src.a);
+
+ res.x = INTRINSIC (_cvts_bf16_bf4) (src.x);
+ if (UNION_CHECK (AVX512F_LEN_QUAR, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162sns-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162sns-2.c
new file mode 100644
index 00000000000..2153a7dcf14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162sns-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#define AVX512F_LEN_QUAR 128
+#include "avx10_3-vcvtbf162sns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#include "avx10_3-vcvtbf162sns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#include "avx10_3-vcvtbf162sns-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162sns-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162sns-2.h
new file mode 100644
index 00000000000..f68d9562e7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162sns-2.h
@@ -0,0 +1,46 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_QUAR / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, __bf16 *s)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_bf16_to_int4 (s[i * 2], true);
+ high = convert_bf16_to_int4 (s[i * 2 + 1], true);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i,sign;
+ UNION_TYPE (AVX512F_LEN_QUAR, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, bf16_bf) src;
+ unsigned char res_ref[SIZE_DST];
+
+ sign = 1;
+ for (i = 0; i < SIZE; i++)
+ {
+ src.a[i] = (__bf16) (sign * (2.5 * (1 << (i % 3))));
+ sign = -sign;
+ }
+
+ CALC(res_ref, src.a);
+
+ res.x = INTRINSIC (_cvts_bf16_epi4) (src.x);
+ if (UNION_CHECK (AVX512F_LEN_QUAR, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162uns-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162uns-2.c
new file mode 100644
index 00000000000..ed29bb9a8ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162uns-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#define AVX512F_LEN_QUAR 128
+#include "avx10_3-vcvtbf162uns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#include "avx10_3-vcvtbf162uns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#include "avx10_3-vcvtbf162uns-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162uns-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162uns-2.h
new file mode 100644
index 00000000000..85f81c2341f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbf162uns-2.h
@@ -0,0 +1,42 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_QUAR / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, __bf16 *s)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_bf16_to_int4 (s[i * 2], false);
+ high = convert_bf16_to_int4 (s[i * 2 + 1], false);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN_QUAR, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, bf16_bf) src;
+ unsigned char res_ref[SIZE_DST];
+
+ for (i = 0; i < SIZE; i++)
+ src.a[i] = (__bf16) (1.25 * (1 << (i % 5)));
+
+ CALC(res_ref, src.a);
+
+ res.x = INTRINSIC (_cvts_bf16_epu4) (src.x);
+ if (UNION_CHECK (AVX512F_LEN_QUAR, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasbf162bf4s-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasbf162bf4s-2.c
new file mode 100644
index 00000000000..02eacebd984
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasbf162bf4s-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#define AVX512F_LEN_QUAR 128
+#include "avx10_3-vcvtbiasbf162bf4s-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#include "avx10_3-vcvtbiasbf162bf4s-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#include "avx10_3-vcvtbiasbf162bf4s-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasbf162bf4s-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasbf162bf4s-2.h
new file mode 100644
index 00000000000..1d33a1fad8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasbf162bf4s-2.h
@@ -0,0 +1,49 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_QUAR / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, unsigned char *s1, __bf16 *s2)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_bf16_to_bf4_bias (s2[i * 2], s1[i * 4]);
+ high = convert_bf16_to_bf4_bias (s2[i * 2 + 1], s1[i * 4 + 2]);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i,sign;
+ UNION_TYPE (AVX512F_LEN_QUAR, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, i_ub) src1;
+ UNION_TYPE (AVX512F_LEN, bf16_bf) src2;
+ unsigned char res_ref[SIZE_DST];
+
+ sign = 1;
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i * 2] = (i % 7) + (1 << (i / 5));
+ src1.a[i * 2 + 1] = (i % 5) + (1 << (i / 7));
+ src2.a[i] = (__bf16) (sign * (2.5 * (1 << (i % 3))));
+ sign = -sign;
+ }
+
+ CALC(res_ref, src1.a, src2.a);
+
+ res.x = INTRINSIC (_cvts_biasbf16_bf4) (src1.x, src2.x);
+ if (UNION_CHECK (AVX512F_LEN_QUAR, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasph2bf4s-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasph2bf4s-2.c
new file mode 100644
index 00000000000..ca7108ce0ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasph2bf4s-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#define AVX512F_LEN_QUAR 128
+#include "avx10_3-vcvtbiasph2bf4s-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#include "avx10_3-vcvtbiasph2bf4s-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#include "avx10_3-vcvtbiasph2bf4s-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasph2bf4s-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasph2bf4s-2.h
new file mode 100644
index 00000000000..fa3ae87a947
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtbiasph2bf4s-2.h
@@ -0,0 +1,49 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_QUAR / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, unsigned char *s1, _Float16 *s2)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_fp16_to_bf4_bias (s2[i * 2], s1[i * 4]);
+ high = convert_fp16_to_bf4_bias (s2[i * 2 + 1], s1[i * 4 + 2]);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i,sign;
+ UNION_TYPE (AVX512F_LEN_QUAR, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, i_ub) src1;
+ UNION_TYPE (AVX512F_LEN, h) src2;
+ unsigned char res_ref[SIZE_DST];
+
+ sign = 1;
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i * 2] = (i % 7) + (1 << (i / 5));
+ src1.a[i * 2 + 1] = (i % 5) + (1 << (i / 7));
+ src2.a[i] = (_Float16) (sign * (2.5 * (1 << (i % 3))));
+ sign = -sign;
+ }
+
+ CALC(res_ref, src1.a, src2.a);
+
+ res.x = INTRINSIC (_cvts_biasph_bf4) (src1.x, src2.x);
+ if (UNION_CHECK (AVX512F_LEN_QUAR, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2bf4s-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2bf4s-2.c
new file mode 100644
index 00000000000..8806a8aa84d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2bf4s-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#define AVX512F_LEN_QUAR 128
+#include "avx10_3-vcvtph2bf4s-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#include "avx10_3-vcvtph2bf4s-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#include "avx10_3-vcvtph2bf4s-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2bf4s-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2bf4s-2.h
new file mode 100644
index 00000000000..ce6cc1021b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2bf4s-2.h
@@ -0,0 +1,46 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_QUAR / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, _Float16 *s)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_fp16_to_bf4 (s[i * 2]);
+ high = convert_fp16_to_bf4 (s[i * 2 + 1]);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i,sign;
+ UNION_TYPE (AVX512F_LEN_QUAR, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, h) src;
+ unsigned char res_ref[SIZE_DST];
+
+ sign = 1;
+ for (i = 0; i < SIZE; i++)
+ {
+ src.a[i] = (_Float16) (sign * (2.5 * (1 << (i % 3))));
+ sign = -sign;
+ }
+
+ CALC(res_ref, src.a);
+
+ res.x = INTRINSIC (_cvts_ph_bf4) (src.x);
+ if (UNION_CHECK (AVX512F_LEN_QUAR, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2sns-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2sns-2.c
new file mode 100644
index 00000000000..6e9dab2b658
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2sns-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#define AVX512F_LEN_QUAR 128
+#include "avx10_3-vcvtph2sns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#include "avx10_3-vcvtph2sns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#include "avx10_3-vcvtph2sns-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2sns-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2sns-2.h
new file mode 100644
index 00000000000..f242f12d82a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2sns-2.h
@@ -0,0 +1,46 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_QUAR / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, _Float16 *s)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_fp16_to_int4 (s[i * 2], true);
+ high = convert_fp16_to_int4 (s[i * 2 + 1], true);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i,sign;
+ UNION_TYPE (AVX512F_LEN_QUAR, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, h) src;
+ unsigned char res_ref[SIZE_DST];
+
+ sign = 1;
+ for (i = 0; i < SIZE; i++)
+ {
+ src.a[i] = (_Float16) (sign * (2.5 * (1 << (i % 3))));
+ sign = -sign;
+ }
+
+ CALC(res_ref, src.a);
+
+ res.x = INTRINSIC (_cvts_ph_epi4) (src.x);
+ if (UNION_CHECK (AVX512F_LEN_QUAR, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2uns-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2uns-2.c
new file mode 100644
index 00000000000..88cc5544002
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2uns-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#define AVX512F_LEN_QUAR 128
+#include "avx10_3-vcvtph2uns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#include "avx10_3-vcvtph2uns-2.h"
+
+#undef AVX512F_LEN
+
+#define AVX512F_LEN 128
+#include "avx10_3-vcvtph2uns-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2uns-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2uns-2.h
new file mode 100644
index 00000000000..207cb0cb3c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vcvtph2uns-2.h
@@ -0,0 +1,42 @@
+#include "avx10-helper.h"
+#include "int4-fp4-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#define SIZE_DST (AVX512F_LEN_QUAR / 8)
+#include "avx512f-mask-type.h"
+
+void
+CALC (unsigned char *r, _Float16 *s)
+{
+ int i;
+ unsigned char low, high;
+
+ for (i = 0; i < SIZE_DST; i++)
+ {
+ r[i] = 0;
+ if (i < SIZE / 2)
+ {
+ low = convert_fp16_to_int4 (s[i * 2], false);
+ high = convert_fp16_to_int4 (s[i * 2 + 1], false);
+ r[i] = (low & 0x0f) | ((high & 0x0f) << 4);
+ }
+ }
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN_QUAR, i_ub) res;
+ UNION_TYPE (AVX512F_LEN, h) src;
+ unsigned char res_ref[SIZE_DST];
+
+ for (i = 0; i < SIZE; i++)
+ src.a[i] = (_Float16) (1.25 * (1 << (i % 5)));
+
+ CALC(res_ref, src.a);
+
+ res.x = INTRINSIC (_cvts_ph_epu4) (src.x);
+ if (UNION_CHECK (AVX512F_LEN_QUAR, i_ub) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/int4-fp4-helper.h
b/gcc/testsuite/gcc.target/i386/int4-fp4-helper.h
new file mode 100644
index 00000000000..0bbb07cd996
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/int4-fp4-helper.h
@@ -0,0 +1,226 @@
+#ifndef INT4_FP4_HELPER_UNCLUDED
+#define INT4_FP4_HELPER_UNCLUDED
+
+#include <stdint.h>
+#include <inttypes.h>
+
+typedef union
+{
+ __bf16 bf16;
+ unsigned short u16;
+} BFloat16Union;
+
+typedef union
+{
+ _Float16 fp16;
+ unsigned short u16;
+} HFloat16Union;
+
+static unsigned char
+convert_bf16_to_bf4 (__bf16 x)
+{
+ BFloat16Union ux = { .bf16 = x };
+ const unsigned short bf16_bias = 127, bf4_bias = 1;
+ unsigned short sign = (ux.u16 & 0x8000) >> 12;
+ unsigned short e_bf16 = (ux.u16 & 0x7f80) >> 7;
+ unsigned short m_bf16 = ux.u16 & 0x007f;
+
+ /* NaN or Infinity. */
+ if (e_bf16 == 0xff)
+ return m_bf16 ? 0x8 : ((0x3 << 1) | 0x1 | sign);
+ /* Zero */
+ if (x == 0)
+ return sign;
+ /* Overflow */
+ else if ((e_bf16 > bf16_bias - bf4_bias + 3)
+ || ((e_bf16 == bf16_bias - bf4_bias + 3)
+ && ((m_bf16 >= 0x60)
+ || ((0x3f >= m_bf16) && (m_bf16 > 0x20)))))
+ return (0x3 << 1) | 0x1 | sign;
+ /* Underflow */
+ else if ((e_bf16 < bf16_bias - bf4_bias - 1)
+ || ((e_bf16 == bf16_bias - bf4_bias - 1) && (m_bf16 == 0x00)))
+ return sign;
+ /* Underflow */
+ else if (((e_bf16 == bf16_bias - bf4_bias - 1) && (m_bf16 != 0x00))
+ || ((e_bf16 == bf16_bias - bf4_bias) && (m_bf16 < 0x40)))
+ return 0x1 | sign;
+ /* Underflow */
+ else if ((e_bf16 == bf16_bias - bf4_bias) && (m_bf16 >= 0x40))
+ return (0x1 << 1) | sign;
+ /* Normal value */
+ else
+ {
+ unsigned short rnex = ux.u16 + 0x1f + (m_bf16 >> 6);
+ unsigned char e = ((rnex & 0x7f80) >> 7) - (bf16_bias - bf4_bias);
+ unsigned char m = (rnex >> 6) & 0x1;
+ return (e << 1) | m | sign;
+ }
+}
+
+static unsigned char
+convert_bf16_to_bf4_bias (__bf16 x, unsigned char b)
+{
+ BFloat16Union ux = { .bf16 = x };
+ const unsigned short bf16_bias = 127, bf4_bias = 1;
+ unsigned short sign = (ux.u16 & 0x8000) >> 12;
+ unsigned short e_bf16 = (ux.u16 & 0x7f80) >> 7;
+ unsigned short m_bf16 = ux.u16 & 0x007f;
+
+ unsigned short x_bias = ux.u16 + (b >> 2);
+ unsigned short e_bf16_bias = (x_bias & 0x7f80) >> 7;
+ unsigned short m_bf16_bias = x_bias & 0x007f;
+
+ /* NaN or Infinity. */
+ if (e_bf16 == 0xff)
+ return m_bf16 ? 0x8 : ((0x3 << 1) | 0x1 | sign);
+ /* Overflow */
+ else if (e_bf16_bias > bf16_bias - bf4_bias + 3)
+ return (0x3 << 1) | 0x1 | sign;
+ /* Input too small or zero */
+ else if (e_bf16 <= bf16_bias - bf4_bias - 9)
+ return sign;
+ /* Underflow */
+ else if (e_bf16_bias <= bf16_bias - bf4_bias)
+ {
+ unsigned char m = m_bf16 | 0x0080;
+ unsigned char sc = bf16_bias - bf4_bias - e_bf16;
+ unsigned char e;
+ m = m + ((b << sc) >> 1);
+ e = (m >> (sc + 8)) & 0x1;
+ m = (m >> (sc + 7)) & 0x1;
+ return (e << 1) | m | sign;
+ }
+ /* Normal value */
+ else
+ {
+ unsigned char e = ((x_bias & 0x7f80) >> 7) - (bf16_bias - bf4_bias);
+ unsigned char m = (m_bf16_bias >> 6) & 0x1;
+ return (e << 1) | m | sign;
+ }
+}
+
+static unsigned char
+convert_bf16_to_int4 (__bf16 x, bool sign)
+{
+ BFloat16Union ux = { .bf16 = x };
+ unsigned short e_bf16 = (ux.u16 & 0x7f80) >> 7;
+
+ if (e_bf16 == 0xff)
+ {
+ unsigned short m_bf16 = ux.u16 & 0x007f;
+ unsigned short s_bf16 = (ux.u16 & 0x8000) >> 15;
+ return sign ? (m_bf16 ? 0 : s_bf16 ? 0x8 : 0x7)
+ : (m_bf16 ? 0 : s_bf16 ? 0x0 : 0xf);
+ }
+
+ int tmp = _mm_cvt_ss2si (_mm_set_ss ((float) x));
+
+ return sign ? (tmp >= 7 ? 0x7 : tmp <= -8 ? 0x8 : tmp & 0xf)
+ : (tmp >= 15 ? 0xf : tmp <= 0 ? 0x0 : tmp & 0xf);
+}
+
+static unsigned char
+convert_fp16_to_bf4 (_Float16 x)
+{
+ HFloat16Union ux = { .fp16 = x };
+ const unsigned short fp16_bias = 15, bf4_bias = 1;
+ unsigned short sign = (ux.u16 & 0x8000) >> 12;
+ unsigned short e_fp16 = (ux.u16 & 0x7c00) >> 10;
+ unsigned short m_fp16 = ux.u16 & 0x03ff;
+
+ /* NaN or Infinity. */
+ if (e_fp16 == 0x1f)
+ return m_fp16 ? 0x8 : ((0x3 << 1) | 0x1 | sign);
+ /* Zero */
+ if (x == 0)
+ return sign;
+ /* Overflow */
+ else if ((e_fp16 > fp16_bias - bf4_bias + 3)
+ || ((e_fp16 == fp16_bias - bf4_bias + 3)
+ && ((m_fp16 >= 0x300)
+ || ((0x1ff >= m_fp16) && (m_fp16 > 0x100)))))
+ return (0x3 << 1) | 0x1 | sign;
+ /* Underflow */
+ else if ((e_fp16 < fp16_bias - bf4_bias - 1)
+ || ((e_fp16 == fp16_bias - bf4_bias - 1) && (m_fp16 == 0x000)))
+ return sign;
+ /* Underflow */
+ else if (((e_fp16 == fp16_bias - bf4_bias - 1) && (m_fp16 != 0x000))
+ || ((e_fp16 == fp16_bias - bf4_bias) && (m_fp16 < 0x200)))
+ return 0x1 | sign;
+ /* Underflow */
+ else if ((e_fp16 == fp16_bias - bf4_bias) && (m_fp16 >= 0x200))
+ return (0x1 << 1) | sign;
+ /* Normal value */
+ else
+ {
+ unsigned short rnex = ux.u16 + 0xff + (m_fp16 >> 9);
+ unsigned char e = ((rnex & 0x7c00) >> 10) - (fp16_bias - bf4_bias);
+ unsigned char m = (rnex >> 9) & 0x1;
+ return (e << 1) | m | sign;
+ }
+}
+
+static unsigned char
+convert_fp16_to_bf4_bias (_Float16 x, unsigned char b)
+{
+ HFloat16Union ux = { .fp16 = x };
+ const unsigned short fp16_bias = 15, bf4_bias = 1;
+ unsigned short sign = (ux.u16 & 0x8000) >> 12;
+ unsigned short e_fp16 = (ux.u16 & 0x7c00) >> 10;
+ unsigned short m_fp16 = ux.u16 & 0x03ff;
+
+ unsigned short x_bias = ux.u16 + (b << 1);
+ unsigned short e_fp16_bias = (x_bias & 0x7c00) >> 10;
+ unsigned short m_fp16_bias = x_bias & 0x03ff;
+
+ /* NaN or Infinity. */
+ if (e_fp16 == 0x1f)
+ return m_fp16 ? 0x8 : ((0x3 << 1) | 0x1 | sign);
+ /* Overflow */
+ else if (e_fp16_bias > fp16_bias - bf4_bias + 3)
+ return (0x3 << 1) | 0x1 | sign;
+ /* Input too small or zero */
+ else if (e_fp16 <= fp16_bias - bf4_bias - 9)
+ return sign;
+ /* Underflow */
+ else if (e_fp16_bias <= fp16_bias - bf4_bias)
+ {
+ unsigned char m = m_fp16 | 0x0400;
+ unsigned char sc = fp16_bias - bf4_bias - e_fp16 + 2;
+ unsigned char e;
+ m = m + (b << sc);
+ e = (m >> (sc + 11)) & 0x1;
+ m = (m >> (sc + 10)) & 0x1;
+ return (e << 1) | m | sign;
+ }
+ /* Normal value */
+ else
+ {
+ unsigned char e = ((x_bias & 0x7c00) >> 10) - (fp16_bias - bf4_bias);
+ unsigned char m = (m_fp16_bias >> 9) & 0x1;
+ return (e << 1) | m | sign;
+ }
+}
+
+static unsigned char
+convert_fp16_to_int4 (_Float16 x, bool sign)
+{
+ HFloat16Union ux = { .fp16 = x };
+ unsigned short e_fp16 = (ux.u16 & 0x7c00) >> 10;
+
+ if (e_fp16 == 0x1f)
+ {
+ unsigned short m_fp16 = ux.u16 & 0x03ff;
+ unsigned short s_fp16 = (ux.u16 & 0x8000) >> 15;
+ return sign ? (m_fp16 ? 0 : s_fp16 ? 0x8 : 0x7)
+ : (m_fp16 ? 0 : s_fp16 ? 0x0 : 0xf);
+ }
+
+ int tmp = _mm_cvt_ss2si (_mm_set_ss ((float) x));
+
+ return sign ? (tmp >= 7 ? 0x7 : tmp <= -8 ? 0x8 : tmp & 0xf)
+ : (tmp >= 15 ? 0xf : tmp <= 0 ? 0x0 : tmp & 0xf);
+}
+#endif
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 3ce06189d2e..9eeedda7acf 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -12094,6 +12094,21 @@ proc check_effective_target_acev1 { } {
} "-macev1" ]
}
+# Return 1 if avx10_3 instructions can be compiled.
+proc check_effective_target_avx10_3 { } {
+ return [check_no_compiler_messages avx10_3 object {
+ typedef int __m128i __attribute__ ((__vector_size__ (16)));
+ typedef _Float16 __v8hf __attribute__ ((__vector_size__ (16)));
+ typedef _Float16 __m128h __attribute__ ((__vector_size__ (16)));
+ __m128i
+ __mm_cvts_ph_bf4 (__m128h __A)
+ {
+ return (__m128i) __builtin_ia32_vcvtph2bf4s128 ((__v8hf) __A);
+ }
+
+ } "-mavx10.3" ]
+}
+
# Return 1 if sse instructions can be compiled.
proc check_effective_target_sse { } {
return [check_no_compiler_messages sse object {
--
2.31.1
