Based on AVX10.2, AVX10.3 will include four parts of instrutrctions,
where AVX10V2AUX has already upstreamed, and the three remaining coming
in the following patches.
AVX10.3 will both imply AVX10.2 and AVX10V2AUX. We will also support
FMV for AVX10.3.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features): Handle
avx10.3.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10_3_SET): New.
(OPTION_MASK_ISA2_AVX10_2_UNSET): Unset AVX10.3.
(OPTION_MASK_ISA2_AVX10V2AUX_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX10_3_UNSET): New.
(ix86_handle_option): Handle avx10.3.
* common/config/i386/i386-cpuinfo.h
(enum processor_features): Add FEATURE_AVX10_3.
(enum processor_priority): Add P_AVX10_3 and P_PROC_AVX10_3.
* common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for
avx10.3.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__AVX10_3__.
* config/i386/i386-isa.def: Add DEF_PTA(AVX10_3).
* config/i386/i386-options.cc (isa2_opts): Add -mavx10.3.
(ix86_valid_target_attribute_inner_p): Handle avx10.3.
* config/i386/i386.opt: Add option -mavx10.3.
* config/i386/i386.opt.urls: Regenerated.
* doc/extend.texi: Document avx10.3.
* doc/invoke.texi: Document -mavx10.3.
* doc/sourcebuild.texi: Document target avx10.3.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Add -mavx10.3.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/avx-1.c: Ditto.
* gcc.target/i386/avx10-check.h: Add avx10.3 check.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/sse-13.c: Add -mavx10.3.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/mvc19.c: New tests.
---
gcc/common/config/i386/cpuinfo.h | 3 +++
gcc/common/config/i386/i386-common.cc | 25 +++++++++++++++++--
gcc/common/config/i386/i386-cpuinfo.h | 3 +++
gcc/common/config/i386/i386-isas.h | 1 +
gcc/config/i386/i386-c.cc | 2 ++
gcc/config/i386/i386-isa.def | 1 +
gcc/config/i386/i386-options.cc | 4 ++-
gcc/config/i386/i386.opt | 5 ++++
gcc/config/i386/i386.opt.urls | 3 +++
gcc/doc/extend.texi | 5 ++++
gcc/doc/invoke.texi | 8 +++++-
gcc/doc/sourcebuild.texi | 21 +++++++++-------
gcc/testsuite/g++.dg/other/i386-2.C | 2 +-
gcc/testsuite/g++.dg/other/i386-3.C | 2 +-
gcc/testsuite/gcc.target/i386/avx-1.c | 2 +-
gcc/testsuite/gcc.target/i386/avx10-check.h | 3 +++
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 ++
gcc/testsuite/gcc.target/i386/mvc19.c | 12 +++++++++
gcc/testsuite/gcc.target/i386/sse-12.c | 2 +-
gcc/testsuite/gcc.target/i386/sse-13.c | 2 +-
gcc/testsuite/gcc.target/i386/sse-14.c | 2 +-
gcc/testsuite/gcc.target/i386/sse-22.c | 4 +--
gcc/testsuite/gcc.target/i386/sse-23.c | 2 +-
23 files changed, 94 insertions(+), 22 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/mvc19.c
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index bc660a803af..d34470d1e92 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -1151,6 +1151,9 @@ get_available_features (struct __processor_model
*cpu_model,
version = ebx & 0xff;
switch (version)
{
+ case 3:
+ set_feature (FEATURE_AVX10_3);
+ /* Fall through. */
case 2:
set_feature (FEATURE_AVX10_2);
/* Fall through. */
diff --git a/gcc/common/config/i386/i386-common.cc
b/gcc/common/config/i386/i386-common.cc
index 49609e48bdf..1fa4a5a6d28 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -146,6 +146,9 @@ along with GCC; see the file COPYING3. If not see
| OPTION_MASK_ISA2_ACEV1)
#define OPTION_MASK_ISA2_AVX10V1AUX_SET \
(OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10V1AUX)
+#define OPTION_MASK_ISA2_AVX10_3_SET \
+ (OPTION_MASK_ISA2_AVX10_2_SET | OPTION_MASK_ISA2_AVX10V2AUX_SET \
+ | OPTION_MASK_ISA2_AVX10_3)
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
@@ -335,18 +338,21 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AVX10_1_UNSET \
(OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET \
| OPTION_MASK_ISA2_AVX10V2AUX_UNSET | OPTION_MASK_ISA2_AVX10V1AUX_UNSET)
-#define OPTION_MASK_ISA2_AVX10_2_UNSET OPTION_MASK_ISA2_AVX10_2
+#define OPTION_MASK_ISA2_AVX10_2_UNSET \
+ (OPTION_MASK_ISA2_AVX10_2 | OPTION_MASK_ISA2_AVX10_3_UNSET)
#define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
#define OPTION_MASK_ISA2_AMX_FP8_UNSET OPTION_MASK_ISA2_AMX_FP8
#define OPTION_MASK_ISA2_MOVRS_UNSET OPTION_MASK_ISA2_MOVRS
#define OPTION_MASK_ISA2_AMX_MOVRS_UNSET OPTION_MASK_ISA2_AMX_MOVRS
#define OPTION_MASK_ISA2_AVX512BMM_UNSET OPTION_MASK_ISA2_AVX512BMM
#define OPTION_MASK_ISA2_AVX10V2AUX_UNSET \
- (OPTION_MASK_ISA2_AVX10V2AUX | OPTION_MASK_ISA2_ACEV1_UNSET)
+ (OPTION_MASK_ISA2_AVX10V2AUX | OPTION_MASK_ISA2_ACEV1_UNSET \
+ | OPTION_MASK_ISA2_AVX10_3_UNSET)
#define OPTION_MASK_ISA2_ACEV1_UNSET OPTION_MASK_ISA2_ACEV1
#define OPTION_MASK_ISA2_AVX10V1AUX_UNSET \
(OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2_UNSET \
| OPTION_MASK_ISA2_ACEV1_UNSET)
+#define OPTION_MASK_ISA2_AVX10_3_UNSET OPTION_MASK_ISA2_AVX10_3
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
@@ -1532,6 +1538,21 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
+ case OPT_mavx10_3:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_3_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_3_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_3_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_3_UNSET;
+ }
+ return true;
+
case OPT_mfma:
if (value)
{
diff --git a/gcc/common/config/i386/i386-cpuinfo.h
b/gcc/common/config/i386/i386-cpuinfo.h
index e75b18bda22..63c87ca8bba 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -161,6 +161,8 @@ enum feature_priority
P_AVX10_2,
P_APX_F,
P_PROC_AVX10_2,
+ P_AVX10_3,
+ P_PROC_AVX10_3,
P_PROC_DYNAMIC
};
@@ -286,6 +288,7 @@ enum processor_features
FEATURE_AVX10V2AUX,
FEATURE_ACEV1,
FEATURE_AVX10V1AUX,
+ FEATURE_AVX10_3,
CPU_FEATURE_MAX
};
diff --git a/gcc/common/config/i386/i386-isas.h
b/gcc/common/config/i386/i386-isas.h
index f4a9fbad6bf..ff2ecbb58a0 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -196,4 +196,5 @@ ISA_NAMES_TABLE_START
ISA_NAMES_TABLE_ENTRY("acev1", FEATURE_ACEV1, P_NONE, "-macev1")
ISA_NAMES_TABLE_ENTRY("avx10v1aux", FEATURE_AVX10V1AUX, P_NONE,
"-mavx10v1aux")
+ ISA_NAMES_TABLE_ENTRY("avx10.3", FEATURE_AVX10_3, P_AVX10_3, "-mavx10.3")
ISA_NAMES_TABLE_END
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index 20f6f820c1c..c90086dbece 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -796,6 +796,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__ACEV1__");
if (isa_flag2 & OPTION_MASK_ISA2_AVX10V1AUX)
def_or_undef (parse_in, "__AVX10V1AUX__");
+ if (isa_flag2 & OPTION_MASK_ISA2_AVX10_3)
+ def_or_undef (parse_in, "__AVX10_3__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index 9803ad6b6f1..1820d22a246 100644
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -128,3 +128,4 @@ DEF_PTA(AVX512BMM)
DEF_PTA(AVX10V2AUX)
DEF_PTA(ACEV1)
DEF_PTA(AVX10V1AUX)
+DEF_PTA(AVX10_3)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index a7b0ad03cad..579289c8c95 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -277,7 +277,8 @@ static struct ix86_target_opts isa2_opts[] =
{ "-mavx512bmm", OPTION_MASK_ISA2_AVX512BMM },
{ "-mavx10v2aux", OPTION_MASK_ISA2_AVX10V2AUX },
{ "-macev1", OPTION_MASK_ISA2_ACEV1 },
- { "-mavx10v1aux", OPTION_MASK_ISA2_AVX10V1AUX }
+ { "-mavx10v1aux", OPTION_MASK_ISA2_AVX10V1AUX },
+ { "-mavx10.3", OPTION_MASK_ISA2_AVX10_3 }
};
static struct ix86_target_opts isa_opts[] =
{
@@ -1145,6 +1146,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree
args, char *p_strings[],
IX86_ATTR_ISA ("avx10v2aux", OPT_mavx10v2aux),
IX86_ATTR_ISA ("acev1", OPT_macev1),
IX86_ATTR_ISA ("avx10v1aux", OPT_mavx10v1aux),
+ IX86_ATTR_ISA ("avx10.3", OPT_mavx10_3),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index e6f4af3a2ec..2c942394076 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1407,3 +1407,8 @@ mavx10v1aux
Target Mask(ISA2_AVX10V1AUX) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
AVX10.1 and AVX10V1AUX built-in functions and code generation.
+
+mavx10.3
+Target Mask(ISA2_AVX10_3) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+AVX10.1, AVX10.2 and AVX10.3 built-in functions and code generation.
diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls
index 304cd67c5aa..33e45c35340 100644
--- a/gcc/config/i386/i386.opt.urls
+++ b/gcc/config/i386/i386.opt.urls
@@ -644,3 +644,6 @@ UrlSuffix(gcc/x86-Options.html#index-macev1)
mavx10v1aux
UrlSuffix(gcc/x86-Options.html#index-mavx10v1aux)
+mavx10.3
+UrlSuffix(gcc/x86-Options.html#index-mavx10_002e3)
+
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index eb8dd1b04f4..b121444ea1b 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9580,6 +9580,11 @@ Enable/disable the generation of the ACEV1 instructions.
@itemx no-avx10v1aux
Enable/disable the generation of the AVX10V1AUX instructions.
+@atindex @code{target("avx10.3")}, x86
+@item avx10.3
+@itemx no-avx10.3
+Enable/Disable the generation of the AVX10.3 instructions.
+
@atindex @code{target("cld")}, x86
@item cld
@itemx no-cld
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ef9cb025c22..ef56222d771 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1555,7 +1555,7 @@ See RS/6000 and PowerPC Options.
-mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
-musermsr -mavx10.1 -mavx10.2 -mamx-avx512 -mmovrs -mamx-movrs
--mavx512bmm -mavx10v2aux -macev1 -mavx10v1aux
+-mavx512bmm -mavx10v2aux -macev1 -mavx10v1aux -mavx10.3
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
@@ -36433,6 +36433,12 @@ AVX10.1 and ACEV1 built-in functions and code
generation.
@item -mavx10v1aux
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
AVX10.1 and AVX10V1AUX built-in functions and code generation.
+
+@opindex mavx10.3
+@opindex mno-avx10.3
+@item -mavx10.3
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+AVX10.1, AVX10.2 and AVX10.3 built-in functions and code generation.
@end table
These additional options are available for the x86 processor family.
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index f24c6f825d2..47ef63c9015 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2707,27 +2707,27 @@ Target supports compiling @code{avx} instructions.
@item avx_runtime
Target supports the execution of @code{avx} instructions.
-@item avx10v2aux
-Target supports the execution of @code{avx10v2aux} instructions.
-
-@item avx10v1aux
-Target supports the execution of @code{avx10v1aux} instructions.
-
@item avx10.1
Target supports the execution of @code{avx10.1} instructions.
@item avx10.2
Target supports the execution of @code{avx10.2} instructions.
+@item avx10.3
+Target supports the execution of @code{avx10.3} instructions.
+
+@item avx10v1aux
+Target supports the execution of @code{avx10v1aux} instructions.
+
+@item avx10v2aux
+Target supports the execution of @code{avx10v2aux} instructions.
+
@item avx2
Target supports compiling @code{avx2} instructions.
@item avx2_runtime
Target supports the execution of @code{avx2} instructions.
-@item avxvnni
-Target supports the execution of @code{avxvnni} instructions.
-
@item avx512f
Target supports compiling @code{avx512f} instructions.
@@ -2743,6 +2743,9 @@ Target supports the execution of @code{avxifma}
instructions.
@item avxneconvert
Target supports the execution of @code{avxneconvert} instructions.
+@item avxvnni
+Target supports the execution of @code{avxvnni} instructions.
+
@item avxvnniint8
Target supports the execution of @code{avxvnniint8} instructions.
diff --git a/gcc/testsuite/g++.dg/other/i386-2.C
b/gcc/testsuite/g++.dg/other/i386-2.C
index d0c6f9990db..9cc4cb3a3d6 100644
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2
-mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp
-mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt
-msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx
-mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize
-mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma
-mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512
-mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2
-mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp
-mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt
-msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx
-mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize
-mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma
-mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512
-mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1 -mavx10.3" } */
/* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib }
} */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
diff --git a/gcc/testsuite/g++.dg/other/i386-3.C
b/gcc/testsuite/g++.dg/other/i386-3.C
index f879c489ac8..cc2e215a511 100644
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1 -mavx10.3" } */
/* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib }
} */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c
b/gcc/testsuite/gcc.target/i386/avx-1.c
index ec21ef4f43c..bf03f43cd79 100644
--- a/gcc/testsuite/gcc.target/i386/avx-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow
-mavx -mavx2 -maes -mpclmul -mgfni -mprefetchi -mavx10.2 -mmovrs -mavx10v2aux
-macev1" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow
-mavx -mavx2 -maes -mpclmul -mgfni -mprefetchi -mavx10.2 -mmovrs -mavx10v2aux
-macev1 -mavx10.3" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx10-check.h
b/gcc/testsuite/gcc.target/i386/avx10-check.h
index 6a1a151f909..bad43b9b38e 100644
--- a/gcc/testsuite/gcc.target/i386/avx10-check.h
+++ b/gcc/testsuite/gcc.target/i386/avx10-check.h
@@ -39,6 +39,9 @@ main ()
if (__builtin_cpu_supports ("avx10.1")
#ifdef AVX10_2
&& __builtin_cpu_supports ("avx10.2")
+#endif
+#ifdef AVX10_3
+ && __builtin_cpu_supports ("avx10.3")
#endif
&& avx10_os_support ())
{
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 0a364ff43d3..9b6c1d07385 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -95,6 +95,7 @@ extern void test_amx_movrs (void)
__attribute__((__target__("amx-movrs")));
extern void test_avx10v2aux (void)
__attribute__((__target__("avx10v2aux")));
extern void test_acev1 (void)
__attribute__((__target__("acev1")));
extern void test_avx10v1aux (void)
__attribute__((__target__("avx10v1aux")));
+extern void test_avx10_3 (void)
__attribute__((__target__("avx10.3")));
extern void test_no_sgx (void)
__attribute__((__target__("no-sgx")));
extern void test_no_avx512vpopcntdq(void)
__attribute__((__target__("no-avx512vpopcntdq")));
@@ -191,6 +192,7 @@ extern void test_no_amx_movrs (void)
__attribute__((__target__("no-amx-movrs"))
extern void test_no_avx10v2aux (void)
__attribute__((__target__("no-avx10v2aux")));
extern void test_no_acev1 (void)
__attribute__((__target__("no-acev1")));
extern void test_no_avx10v1aux (void)
__attribute__((__target__("no-avx10v1aux")));
+extern void test_no_avx10_3 (void)
__attribute__((__target__("no-avx10.3")));
extern void test_arch_nocona (void)
__attribute__((__target__("arch=nocona")));
extern void test_arch_core2 (void)
__attribute__((__target__("arch=core2")));
diff --git a/gcc/testsuite/gcc.target/i386/mvc19.c
b/gcc/testsuite/gcc.target/i386/mvc19.c
new file mode 100644
index 00000000000..5ecdd14c56d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/mvc19.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-ifunc "" } */
+
+/* { dg-final { scan-assembler "foo\.avx10_3\[,@\]" } } */
+
+__attribute__((target_clones("avx10.3","default")))
+int foo ();
+
+int main()
+{
+ return foo();
+}
diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c
b/gcc/testsuite/gcc.target/i386/sse-12.c
index 7d8cb38b561..43938db4834 100644
--- a/gcc/testsuite/gcc.target/i386/sse-12.c
+++ b/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -3,7 +3,7 @@
popcntintrin.h gfniintrin.h and mm_malloc.h are usable
with -O -std=c89 -pedantic-errors. */
/* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex
-mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs
-mamx-movrs -mavx10v2aux -macev1" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex
-mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs
-mamx-movrs -mavx10v2aux -macev1 -mavx10.3" } */
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c
b/gcc/testsuite/gcc.target/i386/sse-13.c
index f43fa8cebf1..7c295ba5452 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt
-mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni
-mpconfig -mwbnoinvd -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8
-mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert
-mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3
-msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs
-mavx10v2aux -macev1" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt
-mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni
-mpconfig -mwbnoinvd -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8
-mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert
-mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3
-msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs
-mavx10v2aux -macev1 -mavx10.3" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c
b/gcc/testsuite/gcc.target/i386/sse-14.c
index 600fe9f3ece..654e2410a56 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx
-mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd
-mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16
-mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx
-mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd
-mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16
-mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1 -mavx10.3" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c
b/gcc/testsuite/gcc.target/i386/sse-22.c
index a4f2613131b..9ecedcd902b 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -119,7 +119,7 @@
#ifndef DIFFERENT_PRAGMAS
-#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1")
+#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1,avx10.3")
#endif
/* Following intrinsics require immediate arguments. They
@@ -236,7 +236,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
/* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */
#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target
("avx,avx2,rdrnd,fsgsbase,f16c,rtm,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1")
+#pragma GCC target
("avx,avx2,rdrnd,fsgsbase,f16c,rtm,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1,avx10.3")
#endif
#include <immintrin.h>
test_1 (_cvtss_sh, unsigned short, float, 1)
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c
b/gcc/testsuite/gcc.target/i386/sse-23.c
index 509cceb21ea..98f42ff041d 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -923,6 +923,6 @@
#define __builtin_ia32_top4mxbssps(W, A, B, C) __builtin_ia32_top4mxbssps (1,
A, B, 9)
#endif
-#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1")
+#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1,avx10.3")
#include <x86intrin.h>
--
2.31.1
