AVX10BMM is using the same instructions sets as AVX512BMM + AVX512VL,
similar as a rebranding. Thus, we simple let AVX10BMM imply AVX512BMM
and AVX10.1. Also I found that the previous 128-bit intrin in
AVX512BMMVL is using _mm128_ as prefix. This is not fitting intrin
naming convention from Intel, where we use _mm_. So we added a new _mm_
prefixed one to fit that to help user to use.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h
(get_available_features): Add AVX10BMM.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10BMM_SET): New.
(OPTION_MASK_ISA2_AVX10_1_UNSET): Unset AVX10BMM.
(OPTION_MASK_ISA2_AVX512BMM_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX10BMM_UNSET): New.
(ix86_handle_option): Handle avx10bmm.
* common/config/i386/i386-cpuinfo.h
(enum processor_features): Add FEATURE_AVX10BMM.
* common/config/i386/i386-isas.h: Ditto.
* config/i386/avx512bmmvlintrin.h
(_mm_mask_bitrev_epi8): New intrin to fit naming convention.
(_mm_maskz_bitrev_epi8): Ditto.
(_mm_bitrev_epi8): Ditto.
* config/i386/cpuid.h (bit_AVX10BMM): New.
* config/i386/i386-c.cc
(ix86_target_macros_internal): Handle AVX10BMM.
* config/i386/i386-isa.def (AVX10BMM): New.
* config/i386/i386-options.cc (isa2_opts): Handle AVX10BMM.
(ix86_valid_target_attribute_inner_p): New.
* config/i386/i386.opt: Add AVX10BMM.
* config/i386/i386.opt.urls: Ditto.
* doc/extend.texi: Ditto.
* doc/invoke.texi: Ditto.
* doc/sourcebuild.texi: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/funcspec-56.inc: Add avx10bmm test.
* gcc.target/i386/avx10bmm-1.c: New test.
---
gcc/common/config/i386/cpuinfo.h | 4 ++
gcc/common/config/i386/i386-common.cc | 25 +++++++++-
gcc/common/config/i386/i386-cpuinfo.h | 1 +
gcc/common/config/i386/i386-isas.h | 1 +
gcc/config/i386/avx512bmmvlintrin.h | 29 ++++++++++++
gcc/config/i386/cpuid.h | 1 +
gcc/config/i386/i386-c.cc | 2 +
gcc/config/i386/i386-isa.def | 1 +
gcc/config/i386/i386-options.cc | 4 +-
gcc/config/i386/i386.opt | 5 ++
gcc/config/i386/i386.opt.urls | 3 ++
gcc/doc/extend.texi | 5 ++
gcc/doc/invoke.texi | 8 +++-
gcc/doc/sourcebuild.texi | 3 ++
gcc/testsuite/gcc.target/i386/avx10bmm-1.c | 46 +++++++++++++++++++
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 +
16 files changed, 136 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/avx10bmm-1.c
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index d34470d1e92..adbbe4afcff 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -1177,6 +1177,10 @@ get_available_features (struct __processor_model
*cpu_model,
set_feature (FEATURE_AVX10V1AUX);
avx10v1aux_set = 1;
}
+ if (ecx & bit_AVX10BMM)
+ {
+ set_feature (FEATURE_AVX10BMM);
+ }
}
}
diff --git a/gcc/common/config/i386/i386-common.cc
b/gcc/common/config/i386/i386-common.cc
index 1fa4a5a6d28..53b8c7fce70 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -149,6 +149,9 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AVX10_3_SET \
(OPTION_MASK_ISA2_AVX10_2_SET | OPTION_MASK_ISA2_AVX10V2AUX_SET \
| OPTION_MASK_ISA2_AVX10_3)
+#define OPTION_MASK_ISA2_AVX10BMM_SET \
+ (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX512BMM_SET \
+ | OPTION_MASK_ISA2_AVX10BMM)
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
@@ -337,14 +340,16 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
#define OPTION_MASK_ISA2_AVX10_1_UNSET \
(OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET \
- | OPTION_MASK_ISA2_AVX10V2AUX_UNSET | OPTION_MASK_ISA2_AVX10V1AUX_UNSET)
+ | OPTION_MASK_ISA2_AVX10V2AUX_UNSET | OPTION_MASK_ISA2_AVX10V1AUX_UNSET \
+ | OPTION_MASK_ISA2_AVX10BMM_UNSET)
#define OPTION_MASK_ISA2_AVX10_2_UNSET \
(OPTION_MASK_ISA2_AVX10_2 | OPTION_MASK_ISA2_AVX10_3_UNSET)
#define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
#define OPTION_MASK_ISA2_AMX_FP8_UNSET OPTION_MASK_ISA2_AMX_FP8
#define OPTION_MASK_ISA2_MOVRS_UNSET OPTION_MASK_ISA2_MOVRS
#define OPTION_MASK_ISA2_AMX_MOVRS_UNSET OPTION_MASK_ISA2_AMX_MOVRS
-#define OPTION_MASK_ISA2_AVX512BMM_UNSET OPTION_MASK_ISA2_AVX512BMM
+#define OPTION_MASK_ISA2_AVX512BMM_UNSET \
+ (OPTION_MASK_ISA2_AVX512BMM | OPTION_MASK_ISA2_AVX10BMM_UNSET)
#define OPTION_MASK_ISA2_AVX10V2AUX_UNSET \
(OPTION_MASK_ISA2_AVX10V2AUX | OPTION_MASK_ISA2_ACEV1_UNSET \
| OPTION_MASK_ISA2_AVX10_3_UNSET)
@@ -353,6 +358,7 @@ along with GCC; see the file COPYING3. If not see
(OPTION_MASK_ISA2_AVX10V1AUX | OPTION_MASK_ISA2_AVX10_2_UNSET \
| OPTION_MASK_ISA2_ACEV1_UNSET)
#define OPTION_MASK_ISA2_AVX10_3_UNSET OPTION_MASK_ISA2_AVX10_3
+#define OPTION_MASK_ISA2_AVX10BMM_UNSET OPTION_MASK_ISA2_AVX10BMM
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
@@ -1553,6 +1559,21 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
+ case OPT_mavx10bmm:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10BMM_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10BMM_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10BMM_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10BMM_UNSET;
+ }
+ return true;
+
case OPT_mfma:
if (value)
{
diff --git a/gcc/common/config/i386/i386-cpuinfo.h
b/gcc/common/config/i386/i386-cpuinfo.h
index 63c87ca8bba..eb591c53519 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -289,6 +289,7 @@ enum processor_features
FEATURE_ACEV1,
FEATURE_AVX10V1AUX,
FEATURE_AVX10_3,
+ FEATURE_AVX10BMM,
CPU_FEATURE_MAX
};
diff --git a/gcc/common/config/i386/i386-isas.h
b/gcc/common/config/i386/i386-isas.h
index ff2ecbb58a0..01517454491 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -197,4 +197,5 @@ ISA_NAMES_TABLE_START
ISA_NAMES_TABLE_ENTRY("avx10v1aux", FEATURE_AVX10V1AUX, P_NONE,
"-mavx10v1aux")
ISA_NAMES_TABLE_ENTRY("avx10.3", FEATURE_AVX10_3, P_AVX10_3, "-mavx10.3")
+ ISA_NAMES_TABLE_ENTRY("avx10bmm", FEATURE_AVX10BMM, P_NONE, "-mavx10bmm")
ISA_NAMES_TABLE_END
diff --git a/gcc/config/i386/avx512bmmvlintrin.h
b/gcc/config/i386/avx512bmmvlintrin.h
index f2f55e99fa2..92860da6939 100644
--- a/gcc/config/i386/avx512bmmvlintrin.h
+++ b/gcc/config/i386/avx512bmmvlintrin.h
@@ -110,6 +110,35 @@ _mm256_bitrev_epi8 (__m256i __A)
(__mmask32) -1);
}
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_bitrev_epi8 (__mmask16 __U, __m128i __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_vbitrevb128_mask ((__v16qi) __A,
+ (__v16qi) __B,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_bitrev_epi8 (__mmask16 __U, __m128i __A)
+{
+ return (__m128i) __builtin_ia32_vbitrevb128_mask ((__v16qi) __A,
+ (__v16qi)(__m128i)
+ _mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_bitrev_epi8 (__m128i __A)
+{
+ return (__m128i) __builtin_ia32_vbitrevb128_mask ((__v16qi) __A,
+ (__v16qi)(__m128i)
+ _mm_undefined_si128 (),
+ (__mmask16) -1);
+}
+
#ifdef __DISABLE_AVX512BMMVL__
#undef __DISABLE_AVX512BMMVL__
#pragma GCC pop_options
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 6f33927b50a..23cddcef6eb 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -173,6 +173,7 @@
/* AVX10 sub leaf (%eax == 0x24, %ecx == 1) */
/* %ecx */
+#define bit_AVX10BMM (1 << 1)
#define bit_AVX10V1AUX (1 << 2)
#define bit_AVX10V2AUX (1 << 3)
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index c90086dbece..fee6fab4af2 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -798,6 +798,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__AVX10V1AUX__");
if (isa_flag2 & OPTION_MASK_ISA2_AVX10_3)
def_or_undef (parse_in, "__AVX10_3__");
+ if (isa_flag2 & OPTION_MASK_ISA2_AVX10BMM)
+ def_or_undef (parse_in, "__AVX10BMM__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index 1820d22a246..9424f3a5667 100644
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -129,3 +129,4 @@ DEF_PTA(AVX10V2AUX)
DEF_PTA(ACEV1)
DEF_PTA(AVX10V1AUX)
DEF_PTA(AVX10_3)
+DEF_PTA(AVX10BMM)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 579289c8c95..261e9fee9a4 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -278,7 +278,8 @@ static struct ix86_target_opts isa2_opts[] =
{ "-mavx10v2aux", OPTION_MASK_ISA2_AVX10V2AUX },
{ "-macev1", OPTION_MASK_ISA2_ACEV1 },
{ "-mavx10v1aux", OPTION_MASK_ISA2_AVX10V1AUX },
- { "-mavx10.3", OPTION_MASK_ISA2_AVX10_3 }
+ { "-mavx10.3", OPTION_MASK_ISA2_AVX10_3 },
+ { "-mavx10bmm", OPTION_MASK_ISA2_AVX10BMM }
};
static struct ix86_target_opts isa_opts[] =
{
@@ -1147,6 +1148,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree
args, char *p_strings[],
IX86_ATTR_ISA ("acev1", OPT_macev1),
IX86_ATTR_ISA ("avx10v1aux", OPT_mavx10v1aux),
IX86_ATTR_ISA ("avx10.3", OPT_mavx10_3),
+ IX86_ATTR_ISA ("avx10bmm", OPT_mavx10bmm),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 2c942394076..0d334550a68 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1412,3 +1412,8 @@ mavx10.3
Target Mask(ISA2_AVX10_3) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
AVX10.1, AVX10.2 and AVX10.3 built-in functions and code generation.
+
+mavx10bmm
+Target Mask(ISA2_AVX10BMM) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+AVX10.1 and AVX10BMM built-in functions and code generation.
diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls
index 33e45c35340..2c1c2e4e1b6 100644
--- a/gcc/config/i386/i386.opt.urls
+++ b/gcc/config/i386/i386.opt.urls
@@ -647,3 +647,6 @@ UrlSuffix(gcc/x86-Options.html#index-mavx10v1aux)
mavx10.3
UrlSuffix(gcc/x86-Options.html#index-mavx10_002e3)
+mavx10bmm
+UrlSuffix(gcc/x86-Options.html#index-mavx10bmm)
+
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index b121444ea1b..ed32b686ec8 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9585,6 +9585,11 @@ Enable/disable the generation of the AVX10V1AUX
instructions.
@itemx no-avx10.3
Enable/Disable the generation of the AVX10.3 instructions.
+@atindex @code{target("avx10bmm")}, x86
+@item avx10bmm
+@itemx no-avx10bmm
+Enable/Disable the generation of the AVX10BMM instructions.
+
@atindex @code{target("cld")}, x86
@item cld
@itemx no-cld
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ef56222d771..443d4f95415 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1555,7 +1555,7 @@ See RS/6000 and PowerPC Options.
-mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
-musermsr -mavx10.1 -mavx10.2 -mamx-avx512 -mmovrs -mamx-movrs
--mavx512bmm -mavx10v2aux -macev1 -mavx10v1aux -mavx10.3
+-mavx512bmm -mavx10v2aux -macev1 -mavx10v1aux -mavx10.3 -mavx10bmm
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
@@ -36439,6 +36439,12 @@ AVX10.1 and AVX10V1AUX built-in functions and code
generation.
@item -mavx10.3
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
AVX10.1, AVX10.2 and AVX10.3 built-in functions and code generation.
+
+@opindex mavx10bmm
+@opindex mno-avx10bmm
+@item -mavx10bmm
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+AVX10.1 and AVX10BMM built-in functions and code generation.
@end table
These additional options are available for the x86 processor family.
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 47ef63c9015..abf0f10f1f1 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2716,6 +2716,9 @@ Target supports the execution of @code{avx10.2}
instructions.
@item avx10.3
Target supports the execution of @code{avx10.3} instructions.
+@item avx10bmm
+Target supports the execution of @code{avx10bmm} instructions.
+
@item avx10v1aux
Target supports the execution of @code{avx10v1aux} instructions.
diff --git a/gcc/testsuite/gcc.target/i386/avx10bmm-1.c
b/gcc/testsuite/gcc.target/i386/avx10bmm-1.c
new file mode 100644
index 00000000000..64e1ab51e54
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10bmm-1.c
@@ -0,0 +1,46 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10bmm -O2" } */
+/* { dg-final { scan-assembler-times "vbmacor16x16x16\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbmacxor16x16x16\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbmacor16x16x16\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbmacxor16x16x16\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbitrevb\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbitrevb\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbitrevb\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbitrevb\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbitrevb\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbitrevb\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbitrevb\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbitrevb\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vbitrevb\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i x512,y512,z512;
+volatile __m256i x256,y256,z256;
+volatile __m128i x128,y128,z128;
+volatile __mmask64 m64;
+volatile __mmask32 m32;
+volatile __mmask16 m16;
+
+void extern
+avx10bmm_test (void)
+{
+ x256 = _mm256_bmacor16x16x16 (x256, y256, z256);
+ x512 = _mm512_bmacor16x16x16 (x512, y512, z512);
+
+ x256 = _mm256_bmacxor16x16x16 (x256, y256, z256);
+ x512 = _mm512_bmacxor16x16x16 (x512, y512, z512);
+
+ x128 = _mm_bitrev_epi8 (x128);
+ x128 = _mm_mask_bitrev_epi8 (m16, x128, y128);
+ x128 = _mm_maskz_bitrev_epi8 (m16, y128);
+
+ x256 = _mm256_bitrev_epi8 (x256);
+ x256 = _mm256_mask_bitrev_epi8 (m32, x256, y256);
+ x256 = _mm256_maskz_bitrev_epi8 (m32, y256);
+
+ x512 = _mm512_bitrev_epi8 (x512);
+ x512 = _mm512_mask_bitrev_epi8 (m64, x512, y512);
+ x512 = _mm512_maskz_bitrev_epi8 (m64, x512);
+}
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 9b6c1d07385..7d2653951c1 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -96,6 +96,7 @@ extern void test_avx10v2aux (void)
__attribute__((__target__("avx10v2aux")));
extern void test_acev1 (void)
__attribute__((__target__("acev1")));
extern void test_avx10v1aux (void)
__attribute__((__target__("avx10v1aux")));
extern void test_avx10_3 (void)
__attribute__((__target__("avx10.3")));
+extern void test_avx10bmm (void)
__attribute__((__target__("avx10bmm")));
extern void test_no_sgx (void)
__attribute__((__target__("no-sgx")));
extern void test_no_avx512vpopcntdq(void)
__attribute__((__target__("no-avx512vpopcntdq")));
@@ -193,6 +194,7 @@ extern void test_no_avx10v2aux (void)
__attribute__((__target__("no-avx10v2aux"
extern void test_no_acev1 (void)
__attribute__((__target__("no-acev1")));
extern void test_no_avx10v1aux (void)
__attribute__((__target__("no-avx10v1aux")));
extern void test_no_avx10_3 (void)
__attribute__((__target__("no-avx10.3")));
+extern void test_no_avx10bmm (void)
__attribute__((__target__("no-avx10bmm")));
extern void test_arch_nocona (void)
__attribute__((__target__("arch=nocona")));
extern void test_arch_core2 (void)
__attribute__((__target__("arch=core2")));
--
2.31.1
