128 bit vpinterleave shares the same functionality with vpunpck, but
only EVEX encoding available. This means if we use 128 bit vpinterleave,
we will always have more or equal codesize. So we redirect all 128 bit
vpinterleave to vpunpck.
gcc/ChangeLog:
* config.gcc: Include avx10_3vpinterleaveintrin.h.
* config/i386/i386-builtin.def (BDESC): Handle builtins.
* config/i386/immintrin.h: Include avx10_3vpinterleaveintrin.h.
* config/i386/sse.md (VI12_256): New.
(vec_interleave_highv64qi<mask_name>): Ditto.
(avx10_3_vec_interleave_highv32qi<mask_name>): Ditto.
(vec_interleave_lowv64qi<mask_name>): Ditto.
(avx10_3_vec_interleave_lowv32qi<mask_name>): Ditto.
(vec_interleave_high<mode><mask_name>): Ditto.
(avx10_3_vec_interleave_high<mode><mask_name>): Ditto.
(vec_interleave_low<mode><mask_name>): Ditto.
(avx10_3_vec_interleave_low<mode><mask_name>): Ditto.
* config/i386/avx10_3vpinterleaveintrin.h: New intrin file.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_3-vpinterleave-1.c: New test.
* gcc.target/i386/avx10_3-vpinterleave-3.c: Ditto.
* gcc.target/i386/avx10_3-vpinterleave-4.c: Ditto.
* gcc.target/i386/avx10_3-vpinterleavehbw-2.c: Ditto.
* gcc.target/i386/avx10_3-vpinterleavehbw-2.h: Ditto.
* gcc.target/i386/avx10_3-vpinterleavehwd-2.c: Ditto.
* gcc.target/i386/avx10_3-vpinterleavehwd-2.h: Ditto.
* gcc.target/i386/avx10_3-vpinterleavelbw-2.c: Ditto.
* gcc.target/i386/avx10_3-vpinterleavelbw-2.h: Ditto.
* gcc.target/i386/avx10_3-vpinterleavelwd-2.c: Ditto.
* gcc.target/i386/avx10_3-vpinterleavelwd-2.h: Ditto.
---
gcc/config.gcc | 3 +-
gcc/config/i386/avx10_3vpinterleaveintrin.h | 438 ++++++++++++++++++
gcc/config/i386/i386-builtin.def | 8 +
gcc/config/i386/immintrin.h | 2 +
gcc/config/i386/sse.md | 240 ++++++++++
.../gcc.target/i386/avx10_3-vpinterleave-1.c | 92 ++++
.../gcc.target/i386/avx10_3-vpinterleave-3.c | 31 ++
.../gcc.target/i386/avx10_3-vpinterleave-4.c | 38 ++
.../i386/avx10_3-vpinterleavehb-2.c | 21 +
.../i386/avx10_3-vpinterleavehb-2.h | 52 +++
.../i386/avx10_3-vpinterleavehw-2.c | 21 +
.../i386/avx10_3-vpinterleavehw-2.h | 53 +++
.../i386/avx10_3-vpinterleavelb-2.c | 21 +
.../i386/avx10_3-vpinterleavelb-2.h | 52 +++
.../i386/avx10_3-vpinterleavelw-2.c | 21 +
.../i386/avx10_3-vpinterleavelw-2.h | 52 +++
16 files changed, 1144 insertions(+), 1 deletion(-)
create mode 100644 gcc/config/i386/avx10_3vpinterleaveintrin.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehb-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehb-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehw-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehw-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelb-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelb-2.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelw-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelw-2.h
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 7b0b24796f0..256d80a11d9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -490,7 +490,8 @@ i[34567]86-*-* | x86_64-*-*)
amxavx512intrin.h amxfp8intrin.h movrsintrin.h
amxmovrsintrin.h avx512bmmintrin.h avx512bmmvlintrin.h
avx10v2auxintrin.h avx10v1auxintrin.h acev1intrin.h
- avx10_3int4fp4intrin.h avx10_3cvtbf16intrin.h"
+ avx10_3int4fp4intrin.h avx10_3cvtbf16intrin.h
+ avx10_3vpinterleaveintrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/avx10_3vpinterleaveintrin.h
b/gcc/config/i386/avx10_3vpinterleaveintrin.h
new file mode 100644
index 00000000000..1729e62ddc0
--- /dev/null
+++ b/gcc/config/i386/avx10_3vpinterleaveintrin.h
@@ -0,0 +1,438 @@
+/* Copyright (C) 2026 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+#error "Never use <avx10_3vpinterleaveintrin.h> directly; include
<immintrin.h> instead."
+#endif
+
+#ifndef _AVX10_3VPINTERLEAVEINTRIN_H_INCLUDED
+#define _AVX10_3VPINTERLEAVEINTRIN_H_INCLUDED
+
+#if !defined(__AVX10_3__)
+#pragma GCC push_options
+#pragma GCC target("avx10.3")
+#define __DISABLE_AVX10_3__
+#endif /* __AVX10_3__ */
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_interleavehi_epi8 (__m128i __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpckhbw128_mask ((__v16qi) __A,
+ (__v16qi) __B,
+ (__v16qi)
+ _mm_undefined_si128 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_interleavehi_epi8 (__m128i __W, __mmask16 __U, __m128i __A,
+ __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpckhbw128_mask ((__v16qi) __A,
+ (__v16qi) __B,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_interleavehi_epi8 (__mmask16 __U, __m128i __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpckhbw128_mask ((__v16qi) __A,
+ (__v16qi) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_interleavehi_epi8 (__m256i __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavehb256_mask ((__v32qi) __A,
+ (__v32qi) __B,
+ (__v32qi)
+
_mm256_undefined_si256 (),
+ (__mmask32) -1);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_interleavehi_epi8 (__m256i __W, __mmask32 __U, __m256i __A,
+ __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavehb256_mask ((__v32qi) __A,
+ (__v32qi) __B,
+ (__v32qi) __W,
+ (__mmask32) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_interleavehi_epi8 (__mmask32 __U, __m256i __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavehb256_mask ((__v32qi) __A,
+ (__v32qi) __B,
+ (__v32qi)
+ _mm256_setzero_si256
(),
+ (__mmask32) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_interleavehi_epi8 (__m512i __A, __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavehb512_mask ((__v64qi) __A,
+ (__v64qi) __B,
+ (__v64qi)
+
_mm512_undefined_si512 (),
+ (__mmask64) -1);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_interleavehi_epi8 (__m512i __W, __mmask64 __U, __m512i __A,
+ __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavehb512_mask ((__v64qi) __A,
+ (__v64qi) __B,
+ (__v64qi) __W,
+ (__mmask64) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_interleavehi_epi8 (__mmask64 __U, __m512i __A, __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavehb512_mask ((__v64qi) __A,
+ (__v64qi) __B,
+ (__v64qi)
+ _mm512_setzero_si512
(),
+ (__mmask64) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_interleavelo_epi8 (__m128i __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpcklbw128_mask ((__v16qi) __A,
+ (__v16qi) __B,
+ (__v16qi)
+ _mm_undefined_si128 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_interleavelo_epi8 (__m128i __W, __mmask16 __U, __m128i __A,
+ __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpcklbw128_mask ((__v16qi) __A,
+ (__v16qi) __B,
+ (__v16qi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_interleavelo_epi8 (__mmask16 __U, __m128i __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpcklbw128_mask ((__v16qi) __A,
+ (__v16qi) __B,
+ (__v16qi)
+ _mm_setzero_si128 (),
+ (__mmask16) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_interleavelo_epi8 (__m256i __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavelb256_mask ((__v32qi) __A,
+ (__v32qi) __B,
+ (__v32qi)
+
_mm256_undefined_si256 (),
+ (__mmask32) -1);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_interleavelo_epi8 (__m256i __W, __mmask32 __U, __m256i __A,
+ __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavelb256_mask ((__v32qi) __A,
+ (__v32qi) __B,
+ (__v32qi) __W,
+ (__mmask32) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_interleavelo_epi8 (__mmask32 __U, __m256i __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavelb256_mask ((__v32qi) __A,
+ (__v32qi) __B,
+ (__v32qi)
+ _mm256_setzero_si256
(),
+ (__mmask32) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_interleavelo_epi8 (__m512i __A, __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavelb512_mask ((__v64qi) __A,
+ (__v64qi) __B,
+ (__v64qi)
+
_mm512_undefined_si512 (),
+ (__mmask64) -1);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_interleavelo_epi8 (__m512i __W, __mmask64 __U, __m512i __A,
+ __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavelb512_mask ((__v64qi) __A,
+ (__v64qi) __B,
+ (__v64qi) __W,
+ (__mmask64) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_interleavelo_epi8 (__mmask64 __U, __m512i __A, __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavelb512_mask ((__v64qi) __A,
+ (__v64qi) __B,
+ (__v64qi)
+ _mm512_setzero_si512
(),
+ (__mmask64) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_interleavehi_epi16 (__m128i __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpckhwd128_mask ((__v8hi) __A,
+ (__v8hi) __B,
+ (__v8hi)
+ _mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_interleavehi_epi16 (__m128i __W, __mmask8 __U, __m128i __A,
+ __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpckhwd128_mask ((__v8hi) __A,
+ (__v8hi) __B,
+ (__v8hi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_interleavehi_epi16 (__mmask8 __U, __m128i __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpckhwd128_mask ((__v8hi) __A,
+ (__v8hi) __B,
+ (__v8hi)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_interleavehi_epi16 (__m256i __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavehw256_mask ((__v16hi) __A,
+ (__v16hi) __B,
+ (__v16hi)
+
_mm256_undefined_si256 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_interleavehi_epi16 (__m256i __W, __mmask16 __U, __m256i __A,
+ __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavehw256_mask ((__v16hi) __A,
+ (__v16hi) __B,
+ (__v16hi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_interleavehi_epi16 (__mmask16 __U, __m256i __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavehw256_mask ((__v16hi) __A,
+ (__v16hi) __B,
+ (__v16hi)
+ _mm256_setzero_si256
(),
+ (__mmask16) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_interleavehi_epi16 (__m512i __A, __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavehw512_mask ((__v32hi) __A,
+ (__v32hi) __B,
+ (__v32hi)
+
_mm512_undefined_si512 (),
+ (__mmask32) -1);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_interleavehi_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
+ __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavehw512_mask ((__v32hi) __A,
+ (__v32hi) __B,
+ (__v32hi) __W,
+ (__mmask32) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_interleavehi_epi16 (__mmask32 __U, __m512i __A, __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavehw512_mask ((__v32hi) __A,
+ (__v32hi) __B,
+ (__v32hi)
+ _mm512_setzero_si512
(),
+ (__mmask32) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_interleavelo_epi16 (__m128i __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpcklwd128_mask ((__v8hi) __A,
+ (__v8hi) __B,
+ (__v8hi)
+ _mm_undefined_si128 (),
+ (__mmask8) -1);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_interleavelo_epi16 (__m128i __W, __mmask8 __U, __m128i __A,
+ __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpcklwd128_mask ((__v8hi) __A,
+ (__v8hi) __B,
+ (__v8hi) __W,
+ (__mmask8) __U);
+}
+
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_interleavelo_epi16 (__mmask8 __U, __m128i __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_punpcklwd128_mask ((__v8hi) __A,
+ (__v8hi) __B,
+ (__v8hi)
+ _mm_setzero_si128 (),
+ (__mmask8) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_interleavelo_epi16 (__m256i __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavelw256_mask ((__v16hi) __A,
+ (__v16hi) __B,
+ (__v16hi)
+
_mm256_undefined_si256 (),
+ (__mmask16) -1);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_interleavelo_epi16 (__m256i __W, __mmask16 __U, __m256i __A,
+ __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavelw256_mask ((__v16hi) __A,
+ (__v16hi) __B,
+ (__v16hi) __W,
+ (__mmask16) __U);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_interleavelo_epi16 (__mmask16 __U, __m256i __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vpinterleavelw256_mask ((__v16hi) __A,
+ (__v16hi) __B,
+ (__v16hi)
+ _mm256_setzero_si256
(),
+ (__mmask16) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_interleavelo_epi16 (__m512i __A, __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavelw512_mask ((__v32hi) __A,
+ (__v32hi) __B,
+ (__v32hi)
+
_mm512_undefined_si512 (),
+ (__mmask32) -1);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_interleavelo_epi16 (__m512i __W, __mmask32 __U, __m512i __A,
+ __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavelw512_mask ((__v32hi) __A,
+ (__v32hi) __B,
+ (__v32hi) __W,
+ (__mmask32) __U);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_interleavelo_epi16 (__mmask32 __U, __m512i __A, __m512i __B)
+{
+ return (__m512i) __builtin_ia32_vpinterleavelw512_mask ((__v32hi) __A,
+ (__v32hi) __B,
+ (__v32hi)
+ _mm512_setzero_si512
(),
+ (__mmask32) __U);
+}
+
+#ifdef __DISABLE_AVX10_3__
+#undef __DISABLE_AVX10_3__
+#pragma GCC pop_options
+#endif /* __DISABLE_AVX10_3__ */
+
+#endif /* __AVX10_3VPINTERLEAVEINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index fd80811b773..b4514b28332 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3536,6 +3536,14 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_3,
CODE_FOR_vcvtbf82bf16v32bf_mask, "__builtin_
BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_vcvthf82bf16v8bf_mask,
"__builtin_ia32_vcvthf82bf16128_mask", IX86_BUILTIN_VCVTHF82BF16128_MASK,
UNKNOWN, (int) V8BF_FTYPE_V16QI_V8BF_UQI)
BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_vcvthf82bf16v16bf_mask,
"__builtin_ia32_vcvthf82bf16256_mask", IX86_BUILTIN_VCVTHF82BF16256_MASK,
UNKNOWN, (int) V16BF_FTYPE_V16QI_V16BF_UHI)
BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_vcvthf82bf16v32bf_mask,
"__builtin_ia32_vcvthf82bf16512_mask", IX86_BUILTIN_VCVTHF82BF16512_MASK,
UNKNOWN, (int) V32BF_FTYPE_V32QI_V32BF_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3,
CODE_FOR_avx10_3_vec_interleave_highv32qi_mask,
"__builtin_ia32_vpinterleavehb256_mask", IX86_BUILTIN_VPINTERLEAVEHB256_MASK,
UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_vec_interleave_highv64qi_mask,
"__builtin_ia32_vpinterleavehb512_mask", IX86_BUILTIN_VPINTERLEAVEHB512_MASK,
UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3,
CODE_FOR_avx10_3_vec_interleave_lowv32qi_mask,
"__builtin_ia32_vpinterleavelb256_mask", IX86_BUILTIN_VPINTERLEAVELB256_MASK,
UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_vec_interleave_lowv64qi_mask,
"__builtin_ia32_vpinterleavelb512_mask", IX86_BUILTIN_VPINTERLEAVELB512_MASK,
UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3,
CODE_FOR_avx10_3_vec_interleave_highv16hi_mask,
"__builtin_ia32_vpinterleavehw256_mask", IX86_BUILTIN_VPINTERLEAVEHW256_MASK,
UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_vec_interleave_highv32hi_mask,
"__builtin_ia32_vpinterleavehw512_mask", IX86_BUILTIN_VPINTERLEAVEHW512_MASK,
UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3,
CODE_FOR_avx10_3_vec_interleave_lowv16hi_mask,
"__builtin_ia32_vpinterleavelw256_mask", IX86_BUILTIN_VPINTERLEAVELW256_MASK,
UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI)
+BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_vec_interleave_lowv32hi_mask,
"__builtin_ia32_vpinterleavelw512_mask", IX86_BUILTIN_VPINTERLEAVELW512_MASK,
UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI)
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index bf1cc821372..a80cd1937e4 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -172,4 +172,6 @@
#include <avx10_3cvtbf16intrin.h>
+#include <avx10_3vpinterleaveintrin.h>
+
#endif /* _IMMINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index ed4fb1310cf..b624998d360 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -20151,6 +20151,50 @@
(set_attr "prefix" "orig,<mask_prefix>")
(set_attr "mode" "<sseinsnmode>")])
+(define_insn "vec_interleave_highv64qi<mask_name>"
+ [(set (match_operand:V64QI 0 "register_operand" "=v")
+ (vec_select:V64QI
+ (vec_concat:V128QI
+ (match_operand:V64QI 1 "register_operand" "v")
+ (match_operand:V64QI 2 "nonimmediate_operand" "vm"))
+ (parallel [(const_int 32) (const_int 96)
+ (const_int 33) (const_int 97)
+ (const_int 34) (const_int 98)
+ (const_int 35) (const_int 99)
+ (const_int 36) (const_int 100)
+ (const_int 37) (const_int 101)
+ (const_int 38) (const_int 102)
+ (const_int 39) (const_int 103)
+ (const_int 40) (const_int 104)
+ (const_int 41) (const_int 105)
+ (const_int 42) (const_int 106)
+ (const_int 43) (const_int 107)
+ (const_int 44) (const_int 108)
+ (const_int 45) (const_int 109)
+ (const_int 46) (const_int 110)
+ (const_int 47) (const_int 111)
+ (const_int 48) (const_int 112)
+ (const_int 49) (const_int 113)
+ (const_int 50) (const_int 114)
+ (const_int 51) (const_int 115)
+ (const_int 52) (const_int 116)
+ (const_int 53) (const_int 117)
+ (const_int 54) (const_int 118)
+ (const_int 55) (const_int 119)
+ (const_int 56) (const_int 120)
+ (const_int 57) (const_int 121)
+ (const_int 58) (const_int 122)
+ (const_int 59) (const_int 123)
+ (const_int 60) (const_int 124)
+ (const_int 61) (const_int 125)
+ (const_int 62) (const_int 126)
+ (const_int 63) (const_int 127)])))]
+ "TARGET_AVX10_3"
+ "vpinterleavehb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+ [(set_attr "type" "sselog")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "XI")])
+
(define_insn "avx512bw_interleave_highv64qi<mask_name>"
[(set (match_operand:V64QI 0 "register_operand" "=v")
(vec_select:V64QI
@@ -20195,6 +20239,34 @@
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
+(define_insn "avx10_3_vec_interleave_highv32qi<mask_name>"
+ [(set (match_operand:V32QI 0 "register_operand" "=v")
+ (vec_select:V32QI
+ (vec_concat:V64QI
+ (match_operand:V32QI 1 "register_operand" "v")
+ (match_operand:V32QI 2 "nonimmediate_operand" "vm"))
+ (parallel [(const_int 16) (const_int 48)
+ (const_int 17) (const_int 49)
+ (const_int 18) (const_int 50)
+ (const_int 19) (const_int 51)
+ (const_int 20) (const_int 52)
+ (const_int 21) (const_int 53)
+ (const_int 22) (const_int 54)
+ (const_int 23) (const_int 55)
+ (const_int 24) (const_int 56)
+ (const_int 25) (const_int 57)
+ (const_int 26) (const_int 58)
+ (const_int 27) (const_int 59)
+ (const_int 28) (const_int 60)
+ (const_int 29) (const_int 61)
+ (const_int 30) (const_int 62)
+ (const_int 31) (const_int 63)])))]
+ "TARGET_AVX10_3"
+ "vpinterleavehb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+ [(set_attr "type" "sselog")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "OI")])
+
(define_insn "avx2_interleave_highv32qi<mask_name>"
[(set (match_operand:V32QI 0 "register_operand" "=Yw")
(vec_select:V32QI
@@ -20247,6 +20319,50 @@
(set_attr "prefix" "orig,<mask_prefix>")
(set_attr "mode" "TI")])
+(define_insn "vec_interleave_lowv64qi<mask_name>"
+ [(set (match_operand:V64QI 0 "register_operand" "=v")
+ (vec_select:V64QI
+ (vec_concat:V128QI
+ (match_operand:V64QI 1 "register_operand" "v")
+ (match_operand:V64QI 2 "nonimmediate_operand" "vm"))
+ (parallel [(const_int 0) (const_int 64)
+ (const_int 1) (const_int 65)
+ (const_int 2) (const_int 66)
+ (const_int 3) (const_int 67)
+ (const_int 4) (const_int 68)
+ (const_int 5) (const_int 69)
+ (const_int 6) (const_int 70)
+ (const_int 7) (const_int 71)
+ (const_int 8) (const_int 72)
+ (const_int 9) (const_int 73)
+ (const_int 10) (const_int 74)
+ (const_int 11) (const_int 75)
+ (const_int 12) (const_int 76)
+ (const_int 13) (const_int 77)
+ (const_int 14) (const_int 78)
+ (const_int 15) (const_int 79)
+ (const_int 16) (const_int 80)
+ (const_int 17) (const_int 81)
+ (const_int 18) (const_int 82)
+ (const_int 19) (const_int 83)
+ (const_int 20) (const_int 84)
+ (const_int 21) (const_int 85)
+ (const_int 22) (const_int 86)
+ (const_int 23) (const_int 87)
+ (const_int 24) (const_int 88)
+ (const_int 25) (const_int 89)
+ (const_int 26) (const_int 90)
+ (const_int 27) (const_int 91)
+ (const_int 28) (const_int 92)
+ (const_int 29) (const_int 93)
+ (const_int 30) (const_int 94)
+ (const_int 31) (const_int 95)])))]
+ "TARGET_AVX10_3"
+ "vpinterleavelb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+ [(set_attr "type" "sselog")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "XI")])
+
(define_insn "avx512bw_interleave_lowv64qi<mask_name>"
[(set (match_operand:V64QI 0 "register_operand" "=v")
(vec_select:V64QI
@@ -20291,6 +20407,34 @@
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
+(define_insn "avx10_3_vec_interleave_lowv32qi<mask_name>"
+ [(set (match_operand:V32QI 0 "register_operand" "=v")
+ (vec_select:V32QI
+ (vec_concat:V64QI
+ (match_operand:V32QI 1 "register_operand" "v")
+ (match_operand:V32QI 2 "nonimmediate_operand" "vm"))
+ (parallel [(const_int 0) (const_int 32)
+ (const_int 1) (const_int 33)
+ (const_int 2) (const_int 34)
+ (const_int 3) (const_int 35)
+ (const_int 4) (const_int 36)
+ (const_int 5) (const_int 37)
+ (const_int 6) (const_int 38)
+ (const_int 7) (const_int 39)
+ (const_int 8) (const_int 40)
+ (const_int 9) (const_int 41)
+ (const_int 10) (const_int 42)
+ (const_int 11) (const_int 43)
+ (const_int 12) (const_int 44)
+ (const_int 13) (const_int 45)
+ (const_int 14) (const_int 46)
+ (const_int 15) (const_int 47)])))]
+ "TARGET_AVX10_3"
+ "vpinterleavelb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+ [(set_attr "type" "sselog")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "OI")])
+
(define_insn "avx2_interleave_lowv32qi<mask_name>"
[(set (match_operand:V32QI 0 "register_operand" "=Yw")
(vec_select:V32QI
@@ -20343,6 +20487,34 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
+(define_insn "vec_interleave_high<mode><mask_name>"
+ [(set (match_operand:V32_512 0 "register_operand" "=v")
+ (vec_select:V32_512
+ (vec_concat:<ssedoublevecmode>
+ (match_operand:V32_512 1 "register_operand" "v")
+ (match_operand:V32_512 2 "nonimmediate_operand" "vm"))
+ (parallel [(const_int 16) (const_int 48)
+ (const_int 17) (const_int 49)
+ (const_int 18) (const_int 50)
+ (const_int 19) (const_int 51)
+ (const_int 20) (const_int 52)
+ (const_int 21) (const_int 53)
+ (const_int 22) (const_int 54)
+ (const_int 23) (const_int 55)
+ (const_int 24) (const_int 56)
+ (const_int 25) (const_int 57)
+ (const_int 26) (const_int 58)
+ (const_int 27) (const_int 59)
+ (const_int 28) (const_int 60)
+ (const_int 29) (const_int 61)
+ (const_int 30) (const_int 62)
+ (const_int 31) (const_int 63)])))]
+ "TARGET_AVX10_3"
+ "vpinterleavehw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+ [(set_attr "type" "sselog")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "XI")])
+
(define_insn "avx512bw_interleave_high<mode><mask_name>"
[(set (match_operand:V32_512 0 "register_operand" "=v")
(vec_select:V32_512
@@ -20371,6 +20543,26 @@
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
+(define_insn "avx10_3_vec_interleave_high<mode><mask_name>"
+ [(set (match_operand:V16_256 0 "register_operand" "=v")
+ (vec_select:V16_256
+ (vec_concat:<ssedoublevecmode>
+ (match_operand:V16_256 1 "register_operand" "v")
+ (match_operand:V16_256 2 "nonimmediate_operand" "vm"))
+ (parallel [(const_int 8) (const_int 24)
+ (const_int 9) (const_int 25)
+ (const_int 10) (const_int 26)
+ (const_int 11) (const_int 27)
+ (const_int 12) (const_int 28)
+ (const_int 13) (const_int 29)
+ (const_int 14) (const_int 30)
+ (const_int 15) (const_int 31)])))]
+ "TARGET_AVX10_3"
+ "vpinterleavehw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+ [(set_attr "type" "sselog")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "OI")])
+
(define_insn "avx2_interleave_high<mode><mask_name>"
[(set (match_operand:V16_256 0 "register_operand" "=Yw")
(vec_select:V16_256
@@ -20411,6 +20603,34 @@
(set_attr "prefix" "orig,maybe_vex")
(set_attr "mode" "TI")])
+(define_insn "vec_interleave_low<mode><mask_name>"
+ [(set (match_operand:V32_512 0 "register_operand" "=v")
+ (vec_select:V32_512
+ (vec_concat:<ssedoublevecmode>
+ (match_operand:V32_512 1 "register_operand" "v")
+ (match_operand:V32_512 2 "nonimmediate_operand" "vm"))
+ (parallel [(const_int 0) (const_int 32)
+ (const_int 1) (const_int 33)
+ (const_int 2) (const_int 34)
+ (const_int 3) (const_int 35)
+ (const_int 4) (const_int 36)
+ (const_int 5) (const_int 37)
+ (const_int 6) (const_int 38)
+ (const_int 7) (const_int 39)
+ (const_int 8) (const_int 40)
+ (const_int 9) (const_int 41)
+ (const_int 10) (const_int 42)
+ (const_int 11) (const_int 43)
+ (const_int 12) (const_int 44)
+ (const_int 13) (const_int 45)
+ (const_int 14) (const_int 46)
+ (const_int 15) (const_int 47)])))]
+ "TARGET_AVX10_3"
+ "vpinterleavelw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+ [(set_attr "type" "sselog")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "XI")])
+
(define_insn "<mask_codefor>avx512bw_interleave_low<mode><mask_name>"
[(set (match_operand:V32_512 0 "register_operand" "=v")
(vec_select:V32_512
@@ -20439,6 +20659,26 @@
(set_attr "prefix" "evex")
(set_attr "mode" "XI")])
+(define_insn "avx10_3_vec_interleave_low<mode><mask_name>"
+ [(set (match_operand:V16_256 0 "register_operand" "=v")
+ (vec_select:V16_256
+ (vec_concat:<ssedoublevecmode>
+ (match_operand:V16_256 1 "register_operand" "v")
+ (match_operand:V16_256 2 "nonimmediate_operand" "vm"))
+ (parallel [(const_int 0) (const_int 16)
+ (const_int 1) (const_int 17)
+ (const_int 2) (const_int 18)
+ (const_int 3) (const_int 19)
+ (const_int 4) (const_int 20)
+ (const_int 5) (const_int 21)
+ (const_int 6) (const_int 22)
+ (const_int 7) (const_int 23)])))]
+ "TARGET_AVX10_3"
+ "vpinterleavelw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+ [(set_attr "type" "sselog")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "OI")])
+
(define_insn "avx2_interleave_low<mode><mask_name>"
[(set (match_operand:V16_256 0 "register_operand" "=Yw")
(vec_select:V16_256
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-1.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-1.c
new file mode 100644
index 00000000000..9756b304087
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-1.c
@@ -0,0 +1,92 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10.3 -fno-fuse-ops-with-volatile-access -O2" } */
+/* { dg-final { scan-assembler-times "vpunpckhbw\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpckhbw\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpckhbw\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehb\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehb\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehb\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehb\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehb\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehb\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpcklbw\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpcklbw\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpcklbw\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelb\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelb\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelb\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelb\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelb\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelb\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpckhwd\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpckhwd\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpckhwd\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehw\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehw\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehw\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehw\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehw\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavehw\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpcklwd\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpcklwd\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpunpcklwd\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelw\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelw\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelw\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelw\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelw\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpinterleavelw\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\[^\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[
\\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512i m512i, _m512i, ___m512i;
+volatile __m256i m256i, _m256i, ___m256i;
+volatile __m128i m128i, _m128i, ___m128i;
+volatile __mmask64 m64;
+volatile __mmask32 m32;
+volatile __mmask16 m16;
+volatile __mmask16 m8;
+
+void extern
+avx10_3_test (void)
+{
+ m128i = _mm_interleavehi_epi8 (_m128i, m128i);
+ m128i = _mm_mask_interleavehi_epi8 (_m128i, m16, m128i, ___m128i);
+ m128i = _mm_maskz_interleavehi_epi8 (m16, m128i, _m128i);
+ m256i = _mm256_interleavehi_epi8 (_m256i, m256i);
+ m256i = _mm256_mask_interleavehi_epi8 (_m256i, m32, m256i, ___m256i);
+ m256i = _mm256_maskz_interleavehi_epi8 (m32, m256i, _m256i);
+ m512i = _mm512_interleavehi_epi8 (_m512i, m512i);
+ m512i = _mm512_mask_interleavehi_epi8 (_m512i, m64, m512i, ___m512i);
+ m512i = _mm512_maskz_interleavehi_epi8 (m64, m512i, _m512i);
+
+ m128i = _mm_interleavelo_epi8 (_m128i, m128i);
+ m128i = _mm_mask_interleavelo_epi8 (_m128i, m16, m128i, ___m128i);
+ m128i = _mm_maskz_interleavelo_epi8 (m16, m128i, _m128i);
+ m256i = _mm256_interleavelo_epi8 (_m256i, m256i);
+ m256i = _mm256_mask_interleavelo_epi8 (_m256i, m32, m256i, ___m256i);
+ m256i = _mm256_maskz_interleavelo_epi8 (m32, m256i, _m256i);
+ m512i = _mm512_interleavelo_epi8 (_m512i, m512i);
+ m512i = _mm512_mask_interleavelo_epi8 (_m512i, m64, m512i, ___m512i);
+ m512i = _mm512_maskz_interleavelo_epi8 (m64, m512i, _m512i);
+
+ m128i = _mm_interleavehi_epi16 (_m128i, m128i);
+ m128i = _mm_mask_interleavehi_epi16 (_m128i, m8, m128i, ___m128i);
+ m128i = _mm_maskz_interleavehi_epi16 (m8, m128i, _m128i);
+ m256i = _mm256_interleavehi_epi16 (_m256i, m256i);
+ m256i = _mm256_mask_interleavehi_epi16 (_m256i, m16, m256i, ___m256i);
+ m256i = _mm256_maskz_interleavehi_epi16 (m16, m256i, _m256i);
+ m512i = _mm512_interleavehi_epi16 (_m512i, m512i);
+ m512i = _mm512_mask_interleavehi_epi16 (_m512i, m32, m512i, ___m512i);
+ m512i = _mm512_maskz_interleavehi_epi16 (m32, m512i, _m512i);
+
+ m128i = _mm_interleavelo_epi16 (_m128i, m128i);
+ m128i = _mm_mask_interleavelo_epi16 (_m128i, m8, m128i, ___m128i);
+ m128i = _mm_maskz_interleavelo_epi16 (m8, m128i, _m128i);
+ m256i = _mm256_interleavelo_epi16 (_m256i, m256i);
+ m256i = _mm256_mask_interleavelo_epi16 (_m256i, m16, m256i, ___m256i);
+ m256i = _mm256_maskz_interleavelo_epi16 (m16, m256i, _m256i);
+ m512i = _mm512_interleavelo_epi16 (_m512i, m512i);
+ m512i = _mm512_mask_interleavelo_epi16 (_m512i, m32, m512i, ___m512i);
+ m512i = _mm512_maskz_interleavelo_epi16 (m32, m512i, _m512i);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-3.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-3.c
new file mode 100644
index 00000000000..fac3f7f698a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx10.3 -O2" } */
+/* { dg-final { scan-assembler "vpinterleavehb\[ \\t\]+\[^\n\]*%ymm" } } */
+/* { dg-final { scan-assembler "vpinterleavelb\[ \\t\]+\[^\n\]*%ymm" } } */
+/* { dg-final { scan-assembler "vpinterleavehw\[ \\t\]+\[^\n\]*%ymm" } } */
+/* { dg-final { scan-assembler "vpinterleavelw\[ \\t\]+\[^\n\]*%ymm" } } */
+/* { dg-final { scan-assembler-not "vperm2i128" } } */
+
+#define N 32
+
+void
+__attribute__((noinline))
+foo_b (char *__restrict d, char *__restrict a, char *__restrict b)
+{
+ for (int i = 0; i < N; i++)
+ {
+ d[2 * i] = a[i];
+ d[2 * i + 1] = b[i];
+ }
+}
+
+void
+__attribute__((noinline))
+foo_w (short *__restrict d, short *__restrict a, short *__restrict b)
+{
+ for (int i = 0; i < N / 2; i++)
+ {
+ d[2 * i] = a[i];
+ d[2 * i + 1] = b[i];
+ }
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-4.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-4.c
new file mode 100644
index 00000000000..5e7fe3a068d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleave-4.c
@@ -0,0 +1,38 @@
+/* { dg-do run } */
+/* { dg-options "-mavx10.3 -O2" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#define DO_TEST do_test
+static void do_test (void);
+#include "avx10-check.h"
+
+#include "avx10_3-vpinterleave-3.c"
+
+static void
+do_test (void)
+{
+ char ba[N], bb[N], bd[2 * N];
+ short sa[N / 2], sb[N / 2], sd[N];
+ int i;
+
+ for (i = 0; i < N; i++)
+ {
+ ba[i] = i * 7 + 3;
+ bb[i] = -i * 9 - 5;
+ }
+ foo_b (bd, ba, bb);
+ for (i = 0; i < 2 * N; i++)
+ if (bd[i] != (i % 2 ? bb : ba)[i / 2])
+ abort ();
+
+ for (i = 0; i < N / 2; i++)
+ {
+ sa[i] = i * 3001 + 17;
+ sb[i] = -i * 4093 - 19;
+ }
+ foo_w (sd, sa, sb);
+ for (i = 0; i < N; i++)
+ if (sd[i] != (i % 2 ? sb : sa)[i / 2])
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehb-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehb-2.c
new file mode 100644
index 00000000000..447afdddfb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehb-2.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#include "avx10_3-vpinterleavehb-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vpinterleavehb-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vpinterleavehb-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehb-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehb-2.h
new file mode 100644
index 00000000000..c86e0208cd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehb-2.h
@@ -0,0 +1,52 @@
+#include "avx10-helper.h"
+
+#define SIZE (AVX512F_LEN / 8)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (char *dst, char *src1, char *src2)
+{
+ int i;
+
+ for (i = 0; i < SIZE; i++)
+ if (i % 2)
+ dst[i] = src2[SIZE / 2 + i / 2];
+ else
+ dst[i] = src1[SIZE / 2 + i / 2];
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN, i_b) res1, res2, res3, src1, src2;
+ MASK_TYPE mask = MASK_VALUE;
+ char res_ref[SIZE];
+
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = 10 + 3 * i;
+ src2.a[i] = 20 + 5 * i;
+ }
+
+ for (i = 0; i < SIZE; i++)
+ res2.a[i] = DEFAULT_VALUE;
+
+ CALC (res_ref, src1.a, src2.a);
+
+ res1.x = INTRINSIC (_interleavehi_epi8) (src1.x, src2.x);
+ res2.x = INTRINSIC (_mask_interleavehi_epi8) (res2.x, mask,
+ src1.x, src2.x);
+ res3.x = INTRINSIC (_maskz_interleavehi_epi8) (mask, src1.x, src2.x);
+
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref))
+ abort ();
+
+ MASK_MERGE (i_b) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref))
+ abort ();
+
+ MASK_ZERO (i_b) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehw-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehw-2.c
new file mode 100644
index 00000000000..aab2bc13c94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehw-2.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#include "avx10_3-vpinterleavehw-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vpinterleavehw-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vpinterleavehw-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehw-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehw-2.h
new file mode 100644
index 00000000000..959ab9f9145
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavehw-2.h
@@ -0,0 +1,53 @@
+#include "avx10-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (short *dst, short *src1, short *src2)
+{
+ int i;
+ int high_off = SIZE / 2;
+
+ for (i = 0; i < SIZE; i++)
+ if (i % 2)
+ dst[i] = src2[SIZE / 2 + i / 2];
+ else
+ dst[i] = src1[SIZE / 2 + i / 2];
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN, i_w) res1, res2, res3, src1, src2;
+ MASK_TYPE mask = MASK_VALUE;
+ short res_ref[SIZE];
+
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = 10 + 3 * i;
+ src2.a[i] = 20 + 5 * i;
+ }
+
+ for (i = 0; i < SIZE; i++)
+ res2.a[i] = DEFAULT_VALUE;
+
+ CALC (res_ref, src1.a, src2.a);
+
+ res1.x = INTRINSIC (_interleavehi_epi16) (src1.x, src2.x);
+ res2.x = INTRINSIC (_mask_interleavehi_epi16) (res2.x, mask,
+ src1.x, src2.x);
+ res3.x = INTRINSIC (_maskz_interleavehi_epi16) (mask, src1.x, src2.x);
+
+ if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref))
+ abort ();
+
+ MASK_MERGE (i_w) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_w) (res2, res_ref))
+ abort ();
+
+ MASK_ZERO (i_w) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_w) (res3, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelb-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelb-2.c
new file mode 100644
index 00000000000..9571c249f76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelb-2.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#include "avx10_3-vpinterleavelb-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vpinterleavelb-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vpinterleavelb-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelb-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelb-2.h
new file mode 100644
index 00000000000..6e827bd47db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelb-2.h
@@ -0,0 +1,52 @@
+#include "avx10-helper.h"
+
+#define SIZE (AVX512F_LEN / 8)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (char *dst, char *src1, char *src2)
+{
+ int i;
+
+ for (i = 0; i < SIZE; i++)
+ if (i % 2)
+ dst[i] = src2[i / 2];
+ else
+ dst[i] = src1[i / 2];
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN, i_b) res1, res2, res3, src1, src2;
+ MASK_TYPE mask = MASK_VALUE;
+ char res_ref[SIZE];
+
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = 10 + 3 * i;
+ src2.a[i] = 20 + 5 * i;
+ }
+
+ for (i = 0; i < SIZE; i++)
+ res2.a[i] = DEFAULT_VALUE;
+
+ CALC (res_ref, src1.a, src2.a);
+
+ res1.x = INTRINSIC (_interleavelo_epi8) (src1.x, src2.x);
+ res2.x = INTRINSIC (_mask_interleavelo_epi8) (res2.x, mask,
+ src1.x, src2.x);
+ res3.x = INTRINSIC (_maskz_interleavelo_epi8) (mask, src1.x, src2.x);
+
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref))
+ abort ();
+
+ MASK_MERGE (i_b) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref))
+ abort ();
+
+ MASK_ZERO (i_b) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelw-2.c
b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelw-2.c
new file mode 100644
index 00000000000..be143b73c70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelw-2.c
@@ -0,0 +1,21 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx10.3" } */
+/* { dg-require-effective-target avx10_3 } */
+
+#define AVX10_3
+#include "avx10_3-vpinterleavelw-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vpinterleavelw-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx10_3-vpinterleavelw-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelw-2.h
b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelw-2.h
new file mode 100644
index 00000000000..307424dc7fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_3-vpinterleavelw-2.h
@@ -0,0 +1,52 @@
+#include "avx10-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#include "avx512f-mask-type.h"
+
+static void
+CALC (short *dst, short *src1, short *src2)
+{
+ int i;
+
+ for (i = 0; i < SIZE; i++)
+ if (i % 2)
+ dst[i] = src2[i / 2];
+ else
+ dst[i] = src1[i / 2];
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN, i_w) res1, res2, res3, src1, src2;
+ MASK_TYPE mask = MASK_VALUE;
+ short res_ref[SIZE];
+
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = 10 + 3 * i;
+ src2.a[i] = 20 + 5 * i;
+ }
+
+ for (i = 0; i < SIZE; i++)
+ res2.a[i] = DEFAULT_VALUE;
+
+ CALC (res_ref, src1.a, src2.a);
+
+ res1.x = INTRINSIC (_interleavelo_epi16) (src1.x, src2.x);
+ res2.x = INTRINSIC (_mask_interleavelo_epi16) (res2.x, mask,
+ src1.x, src2.x);
+ res3.x = INTRINSIC (_maskz_interleavelo_epi16) (mask, src1.x, src2.x);
+
+ if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref))
+ abort ();
+
+ MASK_MERGE (i_w) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_w) (res2, res_ref))
+ abort ();
+
+ MASK_ZERO (i_w) (res_ref, mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_w) (res3, res_ref))
+ abort ();
+}
--
2.31.1
