Hi, sorry for the delay of this reply but just returned from paternity leave.
> > Have you had a look at the SH backend? SH cores have a "T Bit" > register, which functions as carry bit, over/underflow, comparison > result and branch condition register. In the SH backend it's treated as > a fixed SImode hard-reg (although BImode would suffice in this case, I > guess). > <sh patterns> I have looked at sh but didn't fully understand how it worked. Your explanation made it clear. > > The predicate is for matching various forms of T bit negation patterns. > > Maybe you could try the same approach for your case. > If your predicate register has multiple independent bit(fields), you > could try defining separate hard-regs for every bit(field). > It sounds that could be what I want. I probably need not different hard-regs but different pseudos (since I have different pseudo regs) at different modes (since the register might be set differently depending of the mode of the comparison). That seems to be the way to go. Cheers, Paulo Matos
