Hi, The gnet-verilog.scm can already allow us to name a bus and connect a bus net to a bus pin on a symbol. For example, you can connect a net, netname=A[0:15] to a pinnumber=B[16:31] of a symbol, and the Verilog netlister will connect them correctly in Verilog netlist.
It is really upto the netlister/bakend-tools how to handle attributes. gEDA flexible attribute handling allows developer to explore efficient ways to process schematic data for various backend tools is one of the best feature of gEDA. I am not familiar with PCB, may be PCB netlister can use similar method as the Verilog netlister? Its unfortunate, "pinnumber" attribute name is used in Verilog netlister. However that is just semantic, no problem, as long as Verilog'er remembers the pinnumber attribute name is really a "pinname" in most other EDA tools nomenclature. Please ignore the above if it is already well known. Best Regards, Paul Tan -----Original Message----- From: DJ Delorie <[EMAIL PROTECTED]> To: [EMAIL PROTECTED] Cc: [email protected] Sent: Tue, 30 Sep 2008 6:21 pm Subject: Re: gEDA-dev: tutorials from the other guys > >Now, if we could name busses that way, and assign them multiple > >pins... > > Elaborate please? I want to name a "pin" something like "A[0-15]" The pin number would be something like "14-18,20,22,25-33" It would attach to a bus directly (inhereting the net name from the pin name) or with a bus "name" (like mapping pins A[0-7] to nets A[1-8]). The netlister would have to trace busses to merge bus-nets (with some guessing about mapping them), and the netlister would have to peel apart the pin "numbers" to assign them to individual nets A0, A1, A2, etc. That would avoid having 16 or 32 individual pins coming out of boxsyms for busses. _______________________________________________ geda-dev mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev _______________________________________________ geda-dev mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
