On Sun, 2008-11-30 at 10:16 -0500, Stuart Brorson wrote: > If you have any final thoughts or suggestions about the SOW, please do > take the time to put your ideas into the wiki page. At some point in > the near future the SOW will freeze.
I don't want to wikify this myself (not without discussion), but this thought sprang to mind. Whilst we're extending support for layer types, blind and buried vias, we ought to consider the increasing popularity of embedded passives. For example, there are processes which build embedded resistors (and possibly capacitors, perhaps even inductors) using special layers which build up or etch away a resistive portion of the board stack-up. We should aim to understand the needs of that kind of process, and allow the possibility that our new revised layer system can support it. This effectively means some footprints for a (resistor, say), are just mechanical data controlling the etch of a resistive layer, and how the metal layers connect to it. http://www.ticertechnologies.com/tech_papers/01_ThinFilm.pdf Best regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) _______________________________________________ geda-dev mailing list geda-dev@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
