Stephen Williams wrote:
Dan McMahill wrote:
****** force/release to ibus[0] commented; expect bit[0] failure *******
--------- force test failed ---------
force to single unassigned wire failed
force to bit[0] of 2-bit bus failed
Glad I has someone test this for me. That was a sample submitted
in a bug report. With the output you sent, I was able to correct
it, I hope. Can you run the attached updated version with the same
set of tools? It looks correct to me now.
------------------------------------------------------------------
Tool: VERILOG-XL 05.10.002-p Oct 8, 2005 18:16:05
Compiling source file "pr529.v"
Highest level modules:
top
--------- force test failed ---------
force did not affect U2 hierarchy
------------------------------------------------------------------
ncverilog: 05.10-p004: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
ncsim> run
--------- force test failed ---------
force did not affect U2 hierarchy
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
------------------------------------------------------------------
The verilog-xl output with DISPLAY defined is attached.
Hope this helps.
-Dan
Tool: VERILOG-XL 05.10.002-p Oct 9, 2005 00:35:00
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Compiling source file "pr529.v"
Highest level modules:
top
time: 0, subbit: x, subbus: xx
time: 0, subbit: z, subbus: xx
expecting bit, bus,ibus to be 1 at T=1
then changing to 0 at T=2
then bit and bus are 0 from T=3 to T=11, while
ibus changes to 2 at T=5 and remains 2 through to T=16
bit changes to 1 at T=12 and remains 1 from then on.
bus changes to 2 at T=12
then 2 from T=13 to T=14
then changing to 3 at T=15
then 3 from T=16 on
ibus changes to 3 at T=17 and remains 3 from then on
time: 0, a: 1, bit: 1, bitna z, b: 01, bus: 01, ibus: 01
time: 1, subbit: 1, subbus: 01
time: 1, subbit: z, subbus: 01
time: 1, a: 1, bit: 1, bitna z, b: 01, bus: 01, ibus: 01
time: 2, subbit: 0, subbus: 00
time: 2, subbit: 0, subbus: 00
time: 2, a: 1, bit: 0, bitna 0, b: 01, bus: 00, ibus: 00
time: 3, subbit: 0, subbus: 00
time: 3, subbit: 0, subbus: 00
time: 3, a: 1, bit: 0, bitna 0, b: 01, bus: 00, ibus: 00
time: 4, subbit: 0, subbus: 00
time: 4, subbit: 0, subbus: 00
time: 4, a: 1, bit: 0, bitna 0, b: 01, bus: 00, ibus: 00
time: 5, subbit: 0, subbus: 00
time: 5, subbit: 0, subbus: 00
time: 5, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10
time: 6, subbit: 0, subbus: 00
time: 6, subbit: 0, subbus: 00
time: 6, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10
time: 7, subbit: 0, subbus: 00
time: 7, subbit: 0, subbus: 00
time: 7, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10
time: 8, subbit: 0, subbus: 00
time: 8, subbit: 0, subbus: 00
time: 8, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10
time: 9, subbit: 0, subbus: 00
time: 9, subbit: 0, subbus: 00
time: 9, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10
time: 10, subbit: 0, subbus: 00
time: 10, subbit: 0, subbus: 00
time: 10, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10
time: 11, subbit: 0, subbus: 00
time: 11, subbit: 0, subbus: 00
time: 11, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10
time: 12, subbit: 1, subbus: 10
time: 12, subbit: 1, subbus: 10
time: 12, a: 1, bit: 1, bitna 1, b: 10, bus: 10, ibus: 10
time: 13, subbit: 1, subbus: 10
time: 13, subbit: 1, subbus: 10
time: 13, a: 1, bit: 1, bitna 1, b: 10, bus: 10, ibus: 10
time: 14, subbit: 1, subbus: 10
time: 14, subbit: 1, subbus: 10
time: 14, a: 1, bit: 1, bitna 1, b: 10, bus: 10, ibus: 10
time: 15, subbit: 1, subbus: 11
time: 15, subbit: 1, subbus: 11
time: 15, a: 1, bit: 1, bitna 1, b: 11, bus: 11, ibus: 10
time: 16, subbit: 1, subbus: 11
time: 16, subbit: 1, subbus: 11
time: 16, a: 1, bit: 1, bitna 1, b: 11, bus: 11, ibus: 10
time: 17, subbit: 1, subbus: 11
time: 17, subbit: 1, subbus: 11
time: 17, a: 1, bit: 1, bitna 1, b: 11, bus: 11, ibus: 11
time: 18, subbit: 1, subbus: 11
time: 18, subbit: 1, subbus: 11
time: 18, a: 1, bit: 1, bitna 1, b: 11, bus: 11, ibus: 11
time: 19, subbit: 1, subbus: 11
time: 19, subbit: 1, subbus: 11
time: 19, a: 1, bit: 1, bitna 1, b: 11, bus: 11, ibus: 11
--------- force test failed ---------
force did not affect U2 hierarchy
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.1 secs to compile + 0.0 secs to link + 0.1 secs in simulation
End of Tool: VERILOG-XL 05.10.002-p Oct 9, 2005 00:35:23
