# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004 # -- Compiling module top # -- Compiling module subtop # # Top level modules: # top # vsim top # Loading work.top # Loading work.subtop # time: 0, subbit: x, subbus: xx # time: 0, subbit: z, subbus: xx # # expecting bit, bus,ibus to be 1 at T=1 # then changing to 0 at T=2 # then bit and bus are 0 from T=3 to T=11, while # ibus changes to 2 at T=5 and remains 2 through to T=16 # bit changes to 1 at T=12 and remains 1 from then on. # bus changes to 2 at T=12 # then 2 from T=13 to T=14 # then changing to 3 at T=15 # then 3 from T=16 on # ibus changes to 3 at T=17 and remains 3 from then on # # time: 0, a: 1, bit: x, bitna z, b: 01, bus: xx, ibus: xx # time: 1, subbit: 1, subbus: 01 # time: 1, subbit: z, subbus: 01 # time: 1, a: 1, bit: 1, bitna z, b: 01, bus: 01, ibus: 01 # time: 2, subbit: 0, subbus: 00 # time: 2, subbit: 0, subbus: 00 # time: 2, a: 1, bit: 0, bitna 0, b: 01, bus: 00, ibus: 00 # time: 3, subbit: 0, subbus: 00 # time: 3, subbit: 0, subbus: 00 # time: 3, a: 1, bit: 0, bitna 0, b: 01, bus: 00, ibus: 00 # time: 4, subbit: 0, subbus: 00 # time: 4, subbit: 0, subbus: 00 # time: 4, a: 1, bit: 0, bitna 0, b: 01, bus: 00, ibus: 00 # time: 5, subbit: 0, subbus: 00 # time: 5, subbit: 0, subbus: 00 # time: 5, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 00 # time: 6, subbit: 0, subbus: 00 # time: 6, subbit: 0, subbus: 00 # time: 6, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10 # time: 7, subbit: 0, subbus: 00 # time: 7, subbit: 0, subbus: 00 # time: 7, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10 # time: 8, subbit: 0, subbus: 00 # time: 8, subbit: 0, subbus: 00 # time: 8, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10 # time: 9, subbit: 0, subbus: 00 # time: 9, subbit: 0, subbus: 00 # time: 9, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10 # time: 10, subbit: 0, subbus: 00 # time: 10, subbit: 0, subbus: 00 # time: 10, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10 # time: 11, subbit: 0, subbus: 00 # time: 11, subbit: 0, subbus: 00 # time: 11, a: 1, bit: 0, bitna 0, b: 10, bus: 00, ibus: 10 # time: 12, subbit: 1, subbus: 10 # time: 12, subbit: 1, subbus: 10 # time: 12, a: 1, bit: 1, bitna 1, b: 10, bus: 10, ibus: 10 # time: 13, subbit: 1, subbus: 10 # time: 13, subbit: 1, subbus: 10 # time: 13, a: 1, bit: 1, bitna 1, b: 10, bus: 10, ibus: 10 # time: 14, subbit: 1, subbus: 10 # time: 14, subbit: 1, subbus: 10 # time: 14, a: 1, bit: 1, bitna 1, b: 10, bus: 10, ibus: 10 # time: 15, subbit: 1, subbus: 10 # time: 15, subbit: 1, subbus: 10 # time: 15, a: 1, bit: 1, bitna 1, b: 11, bus: 10, ibus: 10 # time: 16, subbit: 1, subbus: 11 # time: 16, subbit: 1, subbus: 11 # time: 16, a: 1, bit: 1, bitna 1, b: 11, bus: 11, ibus: 10 # time: 17, subbit: 1, subbus: 11 # time: 17, subbit: 1, subbus: 11 # time: 17, a: 1, bit: 1, bitna 1, b: 11, bus: 11, ibus: 11 # time: 18, subbit: 1, subbus: 11 # time: 18, subbit: 1, subbus: 11 # time: 18, a: 1, bit: 1, bitna 1, b: 11, bus: 11, ibus: 11 # time: 19, subbit: 1, subbus: 11 # time: 19, subbit: 1, subbus: 11 # time: 19, a: 1, bit: 1, bitna 1, b: 11, bus: 11, ibus: 11 # PASSED
Quoting Stephen Williams <[EMAIL PROTECTED]>: > Dan McMahill wrote: > > --------- force test failed --------- > > force did not affect U2 hierarchy > > > > Hope this helps. > > > Arg! Clearly the PR#529 submitter never debugged the test program > that he submitted. I *think* this time we should get a PASSED out > of it from XL. I just want to get this workig properly so I can > get it checked into the ivtest test suite. > > So try again? > > -- > Steve Williams "The woods are lovely, dark and deep. > steve at icarus.com But I have promises to keep, > http://www.icarus.com and lines to code before I sleep, > http://www.picturel.com And lines to code before I sleep." >
