Well having read through some more emails, I realise I used the wrong file
yet again...Just for good measure here are the outputs from the final pr529.v



> verilog pr529.v
Tool:   VERILOG-XL      05.50.002-s   Oct 10, 2005  11:06:52

Copyright (c) 1995-2004 Cadence Design Systems, Inc.  All Rights Reserved.
Unpublished -- rights reserved under the copyright laws of the United States.

Copyright (c) 1995-2004 UNIX Systems Laboratories, Inc.  Reproduced with 
Permission.

THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION
AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC.  USE, DISCLOSURE, OR
REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
CADENCE DESIGN SYSTEMS, INC.
RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 252.227-7013 or
subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
Rights at 48 CFR 52.227-19, as applicable.

                Cadence Design Systems, Inc.
                555 River Oaks Parkway
                San Jose, California  95134

For technical assistance please contact the Cadence Response Center at
1-877-CDS-4911 or send email to [EMAIL PROTECTED]

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Compiling source file "pr529.v"
Highest level modules:
top

PASSED
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.0 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Tool:    VERILOG-XL      05.50.002-s   Oct 10, 2005  11:06:52

> ncverilog pr529.v
ncverilog: 05.50-s003: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
Recompiling... reason: file './pr529.v' is newer than expected.
        expected: Mon Oct 10 11:00:57 2005
        actual:   Mon Oct 10 11:03:53 2005
file: pr529.v
        module worklib.top:v
                errors: 0, warnings: 0
        module worklib.subtop:v
                errors: 0, warnings: 0
                Caching library 'worklib' ....... Done
        Elaborating the design hierarchy:
        Building instance overlay tables: .................... Done
        Generating native compiled code:
                worklib.subtop:v <0x60c77400>
                        streams:   1, words:  1720
                worklib.top:v <0x652b9caf>
                        streams:   6, words:  7495
        Loading native compiled code:     .................... Done
        Building instance specific data structures.
        Design hierarchy summary:
                             Instances  Unique
                Modules:             3       2
                Registers:          11       9
                Scalar wires:        4       -
                Expanded wires:      4       2
                Initial blocks:      5       4
                Cont. assignments:   0       3
        Writing initial simulation snapshot: worklib.top:v
Loading snapshot worklib.top:v .................... Done
ncsim> source /usr/ldv/tools/inca/files/ncsimrc
ncsim> run
PASSED
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit

> vcs pr529.v

                         Chronologic VCS (TM)
               Version 7.2 -- Mon Oct 10 11:07:03 2005
               Copyright (c) 1991-2004 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

Parsing design file 'pr529.v'
Top Level Modules:
       top
No TimeScale specified
Starting vcs inline pass...
2 modules and 0 UDP read.
recompiling module top because:
        This module or some inlined child module(s) has/have been modified.
recompiling module subtop because:
        This module or some inlined child module(s) has/have been modified.
Both modules done.
if [ -x ../simv ]; then chmod -x ../simv; fi
gcc   -o ../simv  5NrI_d.o 5NrIB_d.o N654_1_d.o BJPB_1_d.o SIM_l.o   
/usr/vcs/gui/virsim/linux/vcdplus/vcs7_2/libvirsim.a     
/usr/vcs/linux/lib/libvcsnew.so     /usr/vcs/linux/lib/ctype-stubs_32.a -ldl  
-lc -lm -ldl   
../simv up to date
CPU time: .050 seconds to compile + .100 seconds to link

> simv
Chronologic VCS simulator copyright 1991-2004
Contains Synopsys proprietary information.
Compiler version 7.2; Runtime version 7.2;  Oct 10 11:07 2005

PASSED
           V C S   S i m u l a t i o n   R e p o r t 
Time: 20
CPU Time:      0.010 seconds;       Data structure size:   0.0Mb
Mon Oct 10 11:07:05 2005

Stephen.



> Delivered-To: [EMAIL PROTECTED]
> X-Original-To: geda-dev@seul.org
> Delivered-To: geda-dev@seul.org
> Date: Sun, 09 Oct 2005 08:26:47 -0700
> From: Stephen Williams <[EMAIL PROTECTED]>
> User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.7.12) 
Gecko/20050921
> X-Accept-Language: en-us, en
> MIME-Version: 1.0
> To: geda-dev@seul.org
> Subject: Re: gEDA: Help with sample program
> X-Enigmail-Version: 0.86.0.0
> X-Enigmail-Supports: pgp-inline, pgp-mime
> X-To-Get-Off-This-List: mail [EMAIL PROTECTED], body unsubscribe geda-dev
> 
> Dan McMahill wrote:
> >         --------- force test failed ---------
> > force did not affect U2 hierarchy
> > 
> > Hope this helps.
> 
> 
> Arg! Clearly the PR#529 submitter never debugged the test program
> that he submitted. I *think* this time we should get a PASSED out
> of it from XL. I just want to get this workig properly so I can
> get it checked into the ivtest test suite.
> 
> So try again?
> 
> -- 
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> http://www.icarus.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."

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