Verilog XL :
------------
Tool: VERILOG-XL 05.50.002-s Oct 10, 2005 10:54:08
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Copyright (c) 1995-2004 UNIX Systems Laboratories, Inc. Reproduced with
Permission.
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RESTRICTED RIGHTS LEGEND
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Compiling source file "pr529.v"
Highest level modules:
top
****** force/release to ibus[0] commented; expect bit[0] failure *******
--------- force test failed ---------
force to single unassigned wire failed
force to bit[0] of 2-bit bus failed
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.3 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Tool: VERILOG-XL 05.50.002-s Oct 10, 2005 10:54:11
NC Verilog :
------------
ncverilog: 05.50-s003: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
file: pr529.v
module worklib.top:v
errors: 0, warnings: 0
module worklib.subtop:v
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.subtop:v <0x60c77400>
streams: 1, words: 1703
worklib.top:v <0x388588b9>
streams: 6, words: 6966
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 3 2
Registers: 11 9
Scalar wires: 4 -
Expanded wires: 2 1
Vectored wires: 1 -
Initial blocks: 5 4
Cont. assignments: 0 3
Writing initial simulation snapshot: worklib.top:v
Loading snapshot worklib.top:v .................... Done
ncsim> source /usr/ldv/tools/inca/files/ncsimrc
ncsim> run
****** force/release to ibus[0] commented; expect bit[0] failure *******
--------- force test failed ---------
force to single unassigned wire failed
force to bit[0] of 2-bit bus failed
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
Synopsys VCS :
--------------
Chronologic VCS simulator copyright 1991-2004
Contains Synopsys proprietary information.
Compiler version 7.2; Runtime version 7.2; Oct 10 10:59 2005
****** force/release to ibus[0] commented; expect bit[0] failure *******
--------- force test failed ---------
force to single unassigned wire failed
force to bit[0] of 2-bit bus failed
V C S S i m u l a t i o n R e p o r t
Time: 20
CPU Time: 0.010 seconds; Data structure size: 0.0Mb
Mon Oct 10 10:59:47 2005
Stephen.
> Delivered-To: [EMAIL PROTECTED]
> X-Original-To: geda-dev@seul.org
> Delivered-To: geda-dev@seul.org
> Date: Fri, 07 Oct 2005 18:02:19 -0700
> From: Stephen Williams <[EMAIL PROTECTED]>
> User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.7.12)
Gecko/20050921
> X-Accept-Language: en-us, en
> MIME-Version: 1.0
> To: geda-dev <geda-dev@seul.org>
> Subject: gEDA: Help with sample program
> X-Enigmail-Version: 0.86.0.0
> X-Enigmail-Supports: pgp-inline, pgp-mime
> X-To-Get-Off-This-List: mail [EMAIL PROTECTED], body unsubscribe geda-dev
>
>
> Can someone run the attached program on some commercial Verilog
> compilers? This is from ivl-bugs PR#529, which I have transferred
> to the iverilog sourceforce Request ID 1313366. I want to get some
> outputs from tools to use as a gold output that I can put into the
> ivtest test suite.
>
> Thanks,
>
> --
> Steve Williams "The woods are lovely, dark and deep.
> steve at icarus.com But I have promises to keep,
> http://www.icarus.com and lines to code before I sleep,
> http://www.picturel.com And lines to code before I sleep."
