Hi Andrew Poelstra, On Aug 14, 2010; 10:34am, Andrew Poelstra wrote:
On Sat, Aug 14, 2010 at 03:17:42AM -0400, Paul Tan wrote: >> ...In fact, I would like to see that gEDA can process ANY attributes >> attached to a net in similar fashion as it process ANY attributes >> attached to a symbol currently. >> >I agree, but I'm not sure this would be useful until we find a way >to split nets up into subnets - which is a much more complicated >change. >Otherwise, certain nets (such as power or ground nets), which often >have vastly different characteristics in different sections, would >be difficult to describe. If the "split nets" means BUS, such as "addrBus[63:0]" which can be split into "addrBus[12:0]", "addrBus[15]", etc; or even the notion of Compound BUS such as "addrBus[63:0],ALE,CTRL", it can all be done with the backend scheme code. It really depends on the particular backend netlister implementation. gnet-verilog.scm is the Verilog netlister, which already handle merging and splitting busses, and hierarchy. An example schematic files with generated Verilog netlist can be found in the attached zip file at: http://archives.seul.org/geda/user/Jan-2009/msg00056.html As you can see from the example, the Verilog netlister (gnet-verilog.scm, Gnetlist backend for Verilog, and the helper shell script) takes advantage of lots of the powerful features presented by the gEDA Gnetlist frontend C/SCM functions, and it is able to do much more than other backends in the area of BUS and non-flatten Hierarchy. Hope the above helps. Best Regards, Paul Tan _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
