On Mon, Jan 24, 2011 at 3:56 AM, Stephan Boettcher <[email protected]> wrote: > > You need to invent some 2-pin symbol with some special attributes, and > teach the pcb gnetlist backend(s) to interpret those attributes as a > net-unification bridge. There should also be a convention how that net > should be named in the output.
Most netlist formats have some sort of short devices: - spice - 0V voltage source, - verilog - "assign" (unidirectional) - LVS (Calibre) - "VIRTUAL CONNECT NAME" - LVS (Assura) - "joinNets" Perhaps PCB backend should have something like this as well? I think it is best to deal with these issues explicitly by adding an appropriate device to the schematics. Otherwise the only universally working way of "fixing" this is flattening the design (or playing some tricks with overwriting ports of hierarchical blocks) at netlist time. Just for the record, many other tools flag this kind of a direct pin-pin connection as an error (a short), refusing netlisting such schematics altogether. This may seem like a bit over-restrictive way of dealing with the issue but (1) quite often these connections *are* unintended shorts, (2) the tool itself relies on the fact that there are no cycles in the connectivity (otherwise any "find a net" type of operation would require an exhaustive search of the whole design space, rather than simple a descend down the hierarchy). Andrzej _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
