changeset 212e2449ee80 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=212e2449ee80
description:
inorder: update bpred code
clean up control flow to make it easier to understand
diffstat:
src/cpu/inorder/resource.cc | 6 +-
src/cpu/inorder/resources/bpred_unit.cc | 11 +---
src/cpu/inorder/resources/branch_predictor.cc | 20 ++++----
src/cpu/inorder/resources/execution_unit.cc | 9 ++-
src/cpu/inorder/resources/fetch_seq_unit.cc | 56 ++++++++++++--------------
5 files changed, 47 insertions(+), 55 deletions(-)
diffs (239 lines):
diff -r 95168d713bc9 -r 212e2449ee80 src/cpu/inorder/resource.cc
--- a/src/cpu/inorder/resource.cc Sun Jun 19 21:43:33 2011 -0400
+++ b/src/cpu/inorder/resource.cc Sun Jun 19 21:43:33 2011 -0400
@@ -305,8 +305,10 @@
int req_slot_num = req_ptr->getSlot();
- if (resourceEvent[req_slot_num].scheduled())
- unscheduleEvent(req_slot_num);
+ if (latency > 0) {
+ if (resourceEvent[req_slot_num].scheduled())
+ unscheduleEvent(req_slot_num);
+ }
freeSlot(req_slot_num);
}
diff -r 95168d713bc9 -r 212e2449ee80 src/cpu/inorder/resources/bpred_unit.cc
--- a/src/cpu/inorder/resources/bpred_unit.cc Sun Jun 19 21:43:33 2011 -0400
+++ b/src/cpu/inorder/resources/bpred_unit.cc Sun Jun 19 21:43:33 2011 -0400
@@ -1,3 +1,4 @@
+
/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
@@ -189,10 +190,6 @@
++condPredicted;
pred_taken = BPLookup(predPC.instAddr(), bp_history);
-
- DPRINTF(InOrderBPred, "[tid:%i]: Branch predictor predicted %i "
- "for PC %s\n",
- tid, pred_taken, inst->pcState());
}
PredictorHistory predict_record(inst->seqNum, predPC, pred_taken,
@@ -242,10 +239,6 @@
inst->isUncondCtrl() &&
inst->isDirectCtrl()) {
target = inst->branchTarget();
-
- DPRINTF(InOrderBPred, "[tid:%i]: Setting %s predicted"
- " target to %s.\n",
- tid, inst->pcState(), target);
} else if (BTB.valid(predPC.instAddr(), asid)) {
++BTBHits;
@@ -267,6 +260,8 @@
// Set the PC and the instruction's predicted target.
predPC = target;
}
+ DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Setting Predicted PC to %s.\n",
+ tid, inst->seqNum, predPC);
predHist[tid].push_front(predict_record);
diff -r 95168d713bc9 -r 212e2449ee80
src/cpu/inorder/resources/branch_predictor.cc
--- a/src/cpu/inorder/resources/branch_predictor.cc Sun Jun 19 21:43:33
2011 -0400
+++ b/src/cpu/inorder/resources/branch_predictor.cc Sun Jun 19 21:43:33
2011 -0400
@@ -66,13 +66,19 @@
void
BranchPredictor::execute(int slot_num)
{
- // After this is working, change this to a reinterpret cast
- // for performance considerations
ResourceRequest* bpred_req = reqs[slot_num];
DynInstPtr inst = bpred_req->inst;
ThreadID tid = inst->readTid();
InstSeqNum seq_num = inst->seqNum;
+ if (!inst->isControl()) {
+ DPRINTF(Resource, "Ignoring %s, not a control inst.\n",
+ inst->instName());
+ bpred_req->done();
+ return;
+ }
+
+
switch (bpred_req->cmd)
{
case PredictBranch:
@@ -84,12 +90,6 @@
} else {
TheISA::PCState pred_PC = inst->pcState();
TheISA::advancePC(pred_PC, inst->staticInst);
-#if ISA_HAS_DELAY_SLOT
- // By default set target to NNPC (e.g. PC + 8)
- // so that a not-taken branch will update
- // correctly
- pred_PC.advance();
-#endif
if (inst->isControl()) {
// If not, the pred_PC be updated to pc+8
@@ -111,8 +111,8 @@
}
inst->setPredTarg(pred_PC);
- DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: Predicted PC is "
- "%s.\n", tid, seq_num, pred_PC);
+ DPRINTF(InOrderBPred, "[tid:%i]: [sn:%i]: %s Predicted PC is "
+ "%s.\n", tid, seq_num, inst->instName(), pred_PC);
}
bpred_req->done();
diff -r 95168d713bc9 -r 212e2449ee80 src/cpu/inorder/resources/execution_unit.cc
--- a/src/cpu/inorder/resources/execution_unit.cc Sun Jun 19 21:43:33
2011 -0400
+++ b/src/cpu/inorder/resources/execution_unit.cc Sun Jun 19 21:43:33
2011 -0400
@@ -139,10 +139,11 @@
lastControlTick = curTick();
// Evaluate Branch
+ DPRINTF(IEW, "Pre-Execute %s PC:%s nextPC:%s predPC:%s\n",
inst->instName(), inst->pcState(), inst->readPredTarg());
fault = inst->execute();
executions++;
-
inst->setExecuted();
+ DPRINTF(IEW, "Post-Execute %s PC:%s nextPC:%s predPC:%s\n",
inst->instName(), inst->pcState(), inst->readPredTarg());
if (fault == NoFault) {
// If branch is mispredicted, then signal squash
@@ -160,14 +161,14 @@
inst->setPredTarg(pc);
if (inst->predTaken() && inst->isCondDelaySlot()) {
+ assert(0 && "Not Handling Conditional Delay
Slots (1)");
inst->bdelaySeqNum = seq_num;
-
DPRINTF(InOrderExecute, "[tid:%i]: Conditional"
" branch inst [sn:%i] PC %s mis"
"predicted as taken.\n", tid,
seq_num, inst->pcState());
- } else if (!inst->predTaken() &&
- inst->isCondDelaySlot()) {
+ } else if (!inst->predTaken() &&
inst->isCondDelaySlot()) {
+ assert(0 && "Not Handling Conditional Delay
Slots (2)");
inst->bdelaySeqNum = seq_num;
inst->procDelaySlotOnMispred = true;
diff -r 95168d713bc9 -r 212e2449ee80 src/cpu/inorder/resources/fetch_seq_unit.cc
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc Sun Jun 19 21:43:33
2011 -0400
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc Sun Jun 19 21:43:33
2011 -0400
@@ -111,13 +111,16 @@
{
if (inst->isControl()) {
// If it's a return, then we must wait for resolved address.
+ // The Predictor will mark a return a false as "not taken"
+ // if there is no RAS entry
if (inst->isReturn() && !inst->predTaken()) {
cpu->pipelineStage[stage_num]->
toPrevStages->stageBlock[stage_num][tid] = true;
pcValid[tid] = false;
pcBlockStage[tid] = stage_num;
} else if (inst->isCondDelaySlot() && !inst->predTaken()) {
- // Not-Taken AND Conditional Control
+ assert(0 && "Not Handling Conditional Delay Slot");
+ // Not-Taken AND Conditional Control
DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i]: [PC:%s] "
"Predicted Not-Taken Cond. Delay inst. Skipping "
"delay slot and Updating PC to %s\n",
@@ -138,15 +141,9 @@
"Not-Taken Control "
"inst. updating PC to %s\n", tid, inst->seqNum,
inst->readPredTarg());
-#if ISA_HAS_DELAY_SLOT
- pc[tid] = inst->pcState();
- advancePC(pc[tid], inst->staticInst);
-#endif
} else if (inst->predTaken()) {
// Taken Control
#if ISA_HAS_DELAY_SLOT
- pc[tid] = inst->readPredTarg();
-
DPRINTF(InOrderFetchSeq, "[tid:%i]: [sn:%i] Updating delay"
" slot target to PC %s\n", tid, inst->seqNum,
inst->readPredTarg());
@@ -184,9 +181,6 @@
// Squash In Pipeline Stage
cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
- // Squash inside current resource, so if there needs to be fetching on
- // same cycle the fetch information will be correct.
-
// Schedule Squash Through-out Resource Pool
cpu->resPool->scheduleEvent(
(InOrderCPU::CPUEventType)ResourcePool::SquashAll, inst, 0);
@@ -222,32 +216,32 @@
squashSeqNum[tid] = done_seq_num;
lastSquashCycle[tid] = curTick();
- // If The very next instruction number is the done seq. num,
- // then we haven't seen the delay slot yet ... if it isn't
- // the last done_seq_num then this is the delay slot inst.
- if (cpu->nextInstSeqNum(tid) != done_seq_num &&
- !inst->procDelaySlotOnMispred) {
+ if (inst->isControl()) {
+ // If the next inst. num is greater than done seq num,
+ // then that means we have seen the delay slot
+ assert(cpu->nextInstSeqNum(tid) >= done_seq_num);
+ if (cpu->nextInstSeqNum(tid) > done_seq_num) {
+ // Reset PC
+ pc[tid] = newPC;
- // Reset PC
- pc[tid] = newPC;
#if ISA_HAS_DELAY_SLOT
- TheISA::advancePC(pc[tid], inst->staticInst);
+ // The Pred. Target will be (NPC, NNPC, NNPC+4)
+ // so since we already saw the NPC (i.e. delay slot)
+ // advance one more to get (NNPC, NNPC+4, NNPC+8)
+ TheISA::advancePC(pc[tid], inst->staticInst);
#endif
- DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
- tid, newPC);
+ DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
+ tid, newPC);
+ } else {
+ // If The very next instruction number that needs to be given
+ // out by the CPU is the done seq. num, then we haven't seen
+ // the delay slot instruction yet.
+ assert(ISA_HAS_DELAY_SLOT);
+ pc[tid] = newPC;
+ }
} else {
- assert(ISA_HAS_DELAY_SLOT);
-
- pc[tid] = (inst->procDelaySlotOnMispred) ?
- inst->branchTarget() : newPC;
-
- // Reset PC to Delay Slot Instruction
- if (inst->procDelaySlotOnMispred) {
- // Reset PC
- pc[tid] = newPC;
- }
-
+ pc[tid] = newPC;
}
// Unblock Any Stages Waiting for this information to be updated ...
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