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src/arch/mips/locked_mem.hh <http://reviews.m5sim.org/r/755/#comment1811> seems like the correct fix here is to fix the CP0 state handling and not circumvent it. setMiscReg() by default has some effect that needs to handled/activated the cycle after a misc. reg gets set. we should find the condition in the CP0 code that causes the CPU to halt and fix it. Any ideas on what lines trigger the code to deadlock (isa.cc maybe?) - Korey On 2011-06-21 19:13:08, Deyuan Guo wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/755/ > ----------------------------------------------------------- > > (Updated 2011-06-21 19:13:08) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > The read/setMiscRegNoEffect are declared in inorder_dyn_inst.hh, but not > defined in inorder_dyn_inst.cc. > I hope the definitions can be added for the future use. > ---- > The problem is caused by a MIPS linked load instruction. It make the CP0 halt > then restart. After that, the tick becomes a large number and it says > 'because simulate() limit reached'. > > Korey Sewell told me: > If you get "simulate() reached", that means your system likely deadlocked > as there are no more events on the main event queue. Run w/the cpu progress > interval on to help determine where the CPUs stops committing instructions. > Also, post the locked_mem.hh patch if you want comments on what you are > trying to do to resolve the problem. > > ---- > I change the locked_mem.hh to an old stable version, to avoid the problem > mentioned above. But I know this is not 'fixing the bug', but 'avoiding the > bug'. > > > Diffs > ----- > > src/arch/mips/locked_mem.hh 00766f5b8177 > src/cpu/inorder/inorder_dyn_inst.cc 00766f5b8177 > > Diff: http://reviews.m5sim.org/r/755/diff > > > Testing > ------- > > Only single thread. > > > Thanks, > > Deyuan > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
