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src/arch/mips/isa.cc <http://reviews.m5sim.org/r/755/#comment2465> Thanks for taking the time to debug this this Deyuan. I'm going to take another pass through your patches and hopefully start to get them by the end of the week. - Korey On 2012-01-17 11:49:44, Deyuan Guo wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/755/ > ----------------------------------------------------------- > > (Updated 2012-01-17 11:49:44) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > The read/setMiscRegNoEffect are declared in inorder_dyn_inst.hh, but not > defined in inorder_dyn_inst.cc. > I hope the definitions can be added for the future use. > ---- > The problem is caused by a MIPS linked load instruction. It make the CP0 halt > then restart. After that, the tick becomes a large number and it says > 'because simulate() limit reached'. > > Korey Sewell told me: > If you get "simulate() reached", that means your system likely deadlocked > as there are no more events on the main event queue. Run w/the cpu progress > interval on to help determine where the CPUs stops committing instructions. > Also, post the locked_mem.hh patch if you want comments on what you are > trying to do to resolve the problem. > > ---- > I change the locked_mem.hh to an old stable version, to avoid the problem > mentioned above. But I know this is not 'fixing the bug', but 'avoiding the > bug'. > > > Diffs > ----- > > src/arch/mips/isa.cc a33fd5964e66 > > Diff: http://reviews.m5sim.org/r/755/diff > > > Testing > ------- > > Only single thread. > > > Thanks, > > Deyuan > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
