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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/755/
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(Updated 2012-01-16 07:20:27.328089)
Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan
Binkert.
Changes
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We have to change setMiscReg into setMiscRegNoEffect here, in order to ensure
the correctness of ll/sc instructions.
While it is unnecessary to use readMiscRegNoEffect instead of readMiscReg.
However, I haven't found the root cause of this problem. May be the misc reg
cannot be set more than once in a tick?
Summary
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The read/setMiscRegNoEffect are declared in inorder_dyn_inst.hh, but not
defined in inorder_dyn_inst.cc.
I hope the definitions can be added for the future use.
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The problem is caused by a MIPS linked load instruction. It make the CP0 halt
then restart. After that, the tick becomes a large number and it says 'because
simulate() limit reached'.
Korey Sewell told me:
If you get "simulate() reached", that means your system likely deadlocked
as there are no more events on the main event queue. Run w/the cpu progress
interval on to help determine where the CPUs stops committing instructions.
Also, post the locked_mem.hh patch if you want comments on what you are trying
to do to resolve the problem.
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I change the locked_mem.hh to an old stable version, to avoid the problem
mentioned above. But I know this is not 'fixing the bug', but 'avoiding the
bug'.
Diffs (updated)
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src/arch/mips/locked_mem.hh f348cf78072c
Diff: http://reviews.m5sim.org/r/755/diff
Testing
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Only single thread.
Thanks,
Deyuan
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