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Why is it necessary for the machine to drain before handling an interrupt? This seems like an excessive overhead since all that needs to happen is a redirecting of the fetch stage and the change of a mode bit. Perhaps x86 has more overhead and does need something more extreme. Can we handle that with a fake instruction that has the proper flags set on it? - Nathan On 2011-07-11 05:05:18, Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/780/ > ----------------------------------------------------------- > > (Updated 2011-07-11 05:05:18) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: When waiting to handle an interrupt, let everything drain out. > > Before this change, the commit stage would wait until the ROB and store queue > were empty before recognizing an interrupt. The fetch stage would stop > generating instructions at an appropriate point, so commit would then wait > until a valid time to interrupt the instruction stream. Instructions might be > in flight after fetch but not the in the ROB or store queue (in rename, for > instance), so this change makes commit wait until all in flight instructions > are finished. > > > Diffs > ----- > > src/cpu/o3/commit_impl.hh 9f3fedee88e2 > > Diff: http://reviews.m5sim.org/r/780/diff > > > Testing > ------- > > > Thanks, > > Gabe > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
