The problem Gabe is seeing is related to x86 micro-ops. He is having a race condition between commit redirecting fetch before fetch has finished issuing a macro-op that is doing operations that cannot be interrupted because they can't be replayed safely. For instance updating the stack pointer mid instruction. He is trying not to wait for the pipe to drain as much as he is trying to allow fetch to issue what it needs to before redirecting as soon as possible.
Gabe, your fix seems it would still cause the race condition to occur although less likely to be hit. What if the fetch stage stalls long enough for the instruction queue to drain before its finished issuing all micro-ops from the ROM? In the default O3 model this may be unlikely because its such an aggressive OoO pipe-line, but if you were modelling something like the AMD Bobcat, with its smaller instruction window this fix may not completely eliminate the bug. You may need to do something more aggressive, like have fetch signal commit when its safe to start servicing the interrupt. Geoff On Sat, Jul 16, 2011 at 12:22 PM, Nathan Binkert <[email protected]> wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/780/#review1424 > ----------------------------------------------------------- > > > Why is it necessary for the machine to drain before handling an interrupt? > This seems like an excessive overhead since all that needs to happen is a > redirecting of the fetch stage and the change of a mode bit. Perhaps x86 > has more overhead and does need something more extreme. Can we handle that > with a fake instruction that has the proper flags set on it? > > - Nathan > > > On 2011-07-11 05:05:18, Gabe Black wrote: > > > > ----------------------------------------------------------- > > This is an automatically generated e-mail. To reply, visit: > > http://reviews.m5sim.org/r/780/ > > ----------------------------------------------------------- > > > > (Updated 2011-07-11 05:05:18) > > > > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > > > > Summary > > ------- > > > > O3: When waiting to handle an interrupt, let everything drain out. > > > > Before this change, the commit stage would wait until the ROB and store > queue > > were empty before recognizing an interrupt. The fetch stage would stop > > generating instructions at an appropriate point, so commit would then > wait > > until a valid time to interrupt the instruction stream. Instructions > might be > > in flight after fetch but not the in the ROB or store queue (in rename, > for > > instance), so this change makes commit wait until all in flight > instructions > > are finished. > > > > > > Diffs > > ----- > > > > src/cpu/o3/commit_impl.hh 9f3fedee88e2 > > > > Diff: http://reviews.m5sim.org/r/780/diff > > > > > > Testing > > ------- > > > > > > Thanks, > > > > Gabe > > > > > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
