> The problem Gabe is seeing is related to x86 micro-ops. He is having a race > condition between commit redirecting fetch before fetch has finished issuing > a macro-op that is doing operations that cannot be interrupted because they > can't be replayed safely. For instance updating the stack pointer mid > instruction. He is trying not to wait for the pipe to drain as much as he > is trying to allow fetch to issue what it needs to before redirecting as > soon as possible. I guess the thing I don't understand is, why is commit redirecting fetch? Why isn't an interrupt simply directly redirecting the fetch stage as if there were some sort of "interrupt macroop" in the middle of the fetch stream?
I'll admit that I don't know how it works on x86, but I'm pretty sure that on alpha an interrupt is a fetch stage thing. Steve/Ali, any ideas? Nate _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
