Hi Nilay,
No, x86 locked RMW accesses are different from Alpha/MIPS LL/SC, and they
are not allowed to be interrupted (once the cache begins the sequence).
In the old days, all the gem5 cpu models implemented was LL/SC, and the
LOCKED flag meant LLSC. A while ago we renamed the old LOCKED flag to LLSC
and added a new LOCKED flag that means x86 atomic RMW.
The situation you're observing is that the classic memory system only
implements LLSC and not LOCKED. In contrast, I believe Ruby implements both
LOCKED and LLSC.
Actually one thing I have been meaning to do is add something like:
if (req->isLocked())
warn_once("Classic cache does not implement locked accesses. MP
execution could be wrong!\n")
to the classic cache code so people know that this is the case.
Steve
On Tue, Oct 25, 2011 at 12:58 PM, Nilay Vaish <[email protected]> wrote:
> Hi
>
> I am trying to make the O3 CPU work with Ruby, but I am running in to
> problem with implementation of Locked RMW in Ruby. Currently, when the read
> part of RMW is issued, Ruby puts the block on a special list. The block is
> taken of that list when the write part of RMW is issued. If any other
> processor issues a read / write request for that block in between the RMW's
> read and write operations, the request is delayed till the block is
> unlocked. This means that the RMW can never fail and the write request needs
> to issued always.
>
> Reading the code from the classic memory system, it seems that it allows
> for the block to be given in case some other processor requests for it. This
> means that classic memory system allows RMW to fail.
>
> My question is which of these behavior is actually implemented in x86? As I
> understand LL/SC is allowed to fail in MIPS or Alpha architecture. I would
> assume that same holds true for x86 as well. Is that the case or not?
>
> Thanks
> Nilay
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