Now I have been able to make some progress on the ISA parser. As per my
understanding there are two ways to mark ldstl and stul as non-speculative
and memory barriers.
1. Change the definition in of LdSt and BigLdSt in
src/arch/x86/isa/microops/ldstop.isa so that they take memBar as a flag as
well. Similarly, we change the definition of StoreOp and LoadOp (they
appear in the same file) so that memBar is passed on to the super class's
constructor. Then, in each of the python files that make use of ldstl and
stul, we can add the flags nonSpec and memBar with values True.
2. Change LdSt and BigLdSt as stated in 1. Make changes to
defineMicro{Store/Load}Op definitions so that they take memBar as an
argument and passes it on to the super class' constructor. Change the
definitions of all the microops accordingly. In this case, I think the
python files do not change. But it may mean that we can not change the
microop's flags in different macroops.
If this sounds Greek, I am ready to post patches for these two.
Gabe, what do you say?
One more thing, why did you choose to treat memory flags and instruction
flags in different manner in ldstop.isa?
--
Nilay
On Thu, 27 Oct 2011, Nilay Vaish wrote:
On Thu, 27 Oct 2011, Steve Reinhardt wrote:
Hi Nilay,
I think a memory barrier may not be sufficient... we need to make sure it's
non-speculative as well as ordered (unless we do something more complicated
to deal with a speculative locked read that isn't followed by a write
because it got squashed).
I could not find anything in AMD's manual on locked instruction being
executed non-speculatively. In one of the Intel manuals, it was stated that
read portion is never is issued unless it is ensured that write portion will
also be issued. So that means that we also need mark the instruction as
non-speculative, apart from marking it as a memory barrier.
Gabe is a better reference (the only reference?) for the details of the x86
decoder.
That does not sound good.
Steve
On Thu, Oct 27, 2011 at 8:32 AM, Nilay Vaish <[email protected]> wrote:
I am thinking of marking all the locked instructions with IsMemBarrier.
Where do you think this flag should appear - in locked_opcodes.isa, or in
semaphores.py? I tried adding IsMemBarrier to the instructions in
locked_opcodes.isa, but that does not work. I changed the instruction
format
to BasicOperate, that also does not work.
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