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Review request for Default. Summary ------- x86: Add microop for fence This patch adds a new microop for memory barrier. The microop itself does nothing, but since it is marked as a memory barrier, the O3 CPU should flush all the pending loads and stores before the fence to the memory system. Diffs ----- src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py 5fb918115c07 src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py 5fb918115c07 src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py 5fb918115c07 src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py 5fb918115c07 src/arch/x86/isa/insts/general_purpose/logical.py 5fb918115c07 src/arch/x86/isa/insts/general_purpose/semaphores.py 5fb918115c07 src/arch/x86/isa/microops/fenceop.isa PRE-CREATION src/arch/x86/isa/microops/microops.isa 5fb918115c07 Diff: http://reviews.m5sim.org/r/898/diff Testing ------- Thanks, Nilay _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
