> On 2011-11-01 23:18:27, Gabe Black wrote: > > src/arch/x86/isa/microops/fenceop.isa, line 44 > > <http://reviews.m5sim.org/r/898/diff/1/?file=15394#file15394line44> > > > > You should be able to use BasicExecute, BasicDecode, etc., from > > arch/x86/isa/formats/basic.isa. Since this microop does literally nothing, > > it shouldn't have any unusual requirements other than setting flags > > appropriately. You should be able to do that using all or mostly just the > > Basic templates.
I think using only Basic templates is not possible. The declaration template does not add X86ISA to the declaration, it only adds the class mentioned in the InstObjParam. If I add X86ISA::<> to the InstObjParam, the constructor definition becomes a problem. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/898/#review1632 ----------------------------------------------------------- On 2011-11-02 09:49:06, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/898/ > ----------------------------------------------------------- > > (Updated 2011-11-02 09:49:06) > > > Review request for Default. > > > Summary > ------- > > x86: Add microop for fence > This patch adds a new microop for memory barrier. The microop itself does > nothing, but since it is marked as a memory barrier, the O3 CPU should flush > all the pending loads and stores before the fence to the memory system. > > > Diffs > ----- > > src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py > 5fb918115c07 > > src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py > 5fb918115c07 > src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py > 5fb918115c07 > src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py 5fb918115c07 > src/arch/x86/isa/insts/general_purpose/logical.py 5fb918115c07 > src/arch/x86/isa/insts/general_purpose/semaphores.py 5fb918115c07 > src/arch/x86/isa/microops/specop.isa 5fb918115c07 > > Diff: http://reviews.m5sim.org/r/898/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
