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The placement of the mfence microops looks fine, and the implementation of the microop is probably correct. There are some things to fix, but the substance of this change looks good. As always x86 and o3 are both pretty tricky, so please test carefully once you fixed the issues. src/arch/x86/isa/microops/fenceop.isa <http://reviews.m5sim.org/r/898/#comment2107> If you make this its own file, you should probably use the copyright used for most of the files and assign it to an appropriate organization. I don't think we really have any specific association with HP any more. I would suggest putting this in the specop.isa file. That's for one off, special microops, and I think this fits into that category pretty solidly. src/arch/x86/isa/microops/fenceop.isa <http://reviews.m5sim.org/r/898/#comment2108> You should be able to use BasicExecute, BasicDecode, etc., from arch/x86/isa/formats/basic.isa. Since this microop does literally nothing, it shouldn't have any unusual requirements other than setting flags appropriately. You should be able to do that using all or mostly just the Basic templates. src/arch/x86/isa/microops/fenceop.isa <http://reviews.m5sim.org/r/898/#comment2109> From here down is the only part that you really need to add to specop.isa - Gabe On 2011-11-01 12:57:40, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/898/ > ----------------------------------------------------------- > > (Updated 2011-11-01 12:57:40) > > > Review request for Default. > > > Summary > ------- > > x86: Add microop for fence > This patch adds a new microop for memory barrier. The microop itself does > nothing, but since it is marked as a memory barrier, the O3 CPU should flush > all the pending loads and stores before the fence to the memory system. > > > Diffs > ----- > > src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py > 5fb918115c07 > > src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py > 5fb918115c07 > src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py > 5fb918115c07 > src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py 5fb918115c07 > src/arch/x86/isa/insts/general_purpose/logical.py 5fb918115c07 > src/arch/x86/isa/insts/general_purpose/semaphores.py 5fb918115c07 > src/arch/x86/isa/microops/fenceop.isa PRE-CREATION > src/arch/x86/isa/microops/microops.isa 5fb918115c07 > > Diff: http://reviews.m5sim.org/r/898/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
