> On 2011-11-06 01:15:31, Gabe Black wrote: > > src/cpu/BaseCPU.py, line 192 > > <http://reviews.m5sim.org/r/904/diff/1/?file=15421#file15421line192> > > > > This is wrong. Boiled down, it's saying: > > > > if x86 or arm: > > foo; > > elif x86 or arm: > > bar; > > > > bar will never happen. It's not quite that simple, but that doesn't > > change the nature of the problem. Have you run regressions on this? I > > expect it will cause problems in at least one of x86 or ARM.
No it's saying in x86 or arm and there is a tlb cache specified, then do foo, otherwise if you didn't select a tlb cache in your config do bar - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/904/#review1637 ----------------------------------------------------------- On 2011-11-03 13:30:18, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/904/ > ----------------------------------------------------------- > > (Updated 2011-11-03 13:30:18) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > ARM: Add support for having a TLB cache. > > > Diffs > ----- > > src/cpu/BaseCPU.py 5fb918115c07 > > Diff: http://reviews.m5sim.org/r/904/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
