> On 2011-11-08 11:17:28, Steve Reinhardt wrote: > > src/cpu/BaseCPU.py, line 185 > > <http://reviews.m5sim.org/r/904/diff/1/?file=15421#file15421line185> > > > > Wouldn't it be equivalent to write: > > > > if buildEnv['FULL_SYSTEM'] and buildEnv['TARGET_ISA'] in ['x86', 'arm']: > > if iwc and dwc: > > [stuff] > > else: > > [other stuff] > > > > ?? > > > > Assuming I haven't missed some corner case, this sure seems clearer to > > me. > >
Yes, I agree. I think I see why it's not actually wrong, but now we have experimental proof that it's a bit confusing. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/904/#review1646 ----------------------------------------------------------- On 2011-11-03 13:30:18, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/904/ > ----------------------------------------------------------- > > (Updated 2011-11-03 13:30:18) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > ARM: Add support for having a TLB cache. > > > Diffs > ----- > > src/cpu/BaseCPU.py 5fb918115c07 > > Diff: http://reviews.m5sim.org/r/904/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
