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Does this really implement a post-retirement store buffer, or is this just a pre-retirement store queue? I don't really know anything about this code, but based on my brief scan the store queue looks like it tracks pre-retirement stores. If so, that is very different than a post-retirement store buffer. Furthermore, you need to be careful whether the head of the pre-retirement store queue is speculative or non-speculative. - Brad On 2011-11-15 07:00:31, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/908/ > ----------------------------------------------------------- > > (Updated 2011-11-15 07:00:31) > > > Review request for Default. > > > Summary > ------- > > O3 LSQ: Implement TSO > This patch makes O3's LSQ maintain total order between stores. Essentially > only the store at the head of the store buffer is allowed to be in flight. > Only after that store completes, the next store is issued to the memory > system. > > > Diffs > ----- > > src/cpu/o3/lsq_unit.hh e66a566f2cfa > src/cpu/o3/lsq_unit_impl.hh e66a566f2cfa > > Diff: http://reviews.m5sim.org/r/908/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
