Great. It sounds like you understand the difference. So just to be sure, I assume that the load queue has no split between committed loads and speculative loads, correct? The load queue should only be tracking speculative memory operations.
Brad From: Nilay Vaish [mailto:[email protected]] Sent: Tuesday, November 15, 2011 3:26 PM To: Nilay Vaish; Beckmann, Brad; Default Subject: Re: Review Request: O3 LSQ: Implement TSO This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/908/ On November 15th, 2011, 3:05 p.m., Brad Beckmann wrote: Does this really implement a post-retirement store buffer, or is this just a pre-retirement store queue? I don't really know anything about this code, but based on my brief scan the store queue looks like it tracks pre-retirement stores. If so, that is very different than a post-retirement store buffer. Furthermore, you need to be careful whether the head of the pre-retirement store queue is speculative or non-speculative. Brad, the store queue maintains both speculative and committed stores. My understanding is that once the flag canWB is set to true, the instruction is now free to issue the store to the memory (that is the instruction is now committed). The loop in which I added the condition for checking whether there is a store in flight, is the one used for issuing stores to the memory. Since the loop condition checks whether canWB is true, therefore only non-speculative stores would be issued to the memory system. - Nilay On November 15th, 2011, 7 a.m., Nilay Vaish wrote: Review request for Default. By Nilay Vaish. Updated 2011-11-15 07:00:31 Description O3 LSQ: Implement TSO This patch makes O3's LSQ maintain total order between stores. Essentially only the store at the head of the store buffer is allowed to be in flight. Only after that store completes, the next store is issued to the memory system. Diffs * src/cpu/o3/lsq_unit.hh (e66a566f2cfa) * src/cpu/o3/lsq_unit_impl.hh (e66a566f2cfa) View Diff<http://reviews.m5sim.org/r/908/diff/> _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
