> On 2011-11-15 16:05:29, Ali Saidi wrote: > > src/cpu/o3/lsq_unit_impl.hh, line 773 > > <http://reviews.m5sim.org/r/908/diff/1/?file=15488#file15488line773> > > > > How about we have a parameter to the CPU and have a check that it's set > > for x86. > > Nilay Vaish wrote: > Or we can have it as a trait of an isa just like we have one flag for > memory access alignment. > > Ali Saidi wrote: > But you might want to see how performance changes if you enable it on an > isa with a weaker memory model.
Having #ifdefs is usually bad, and making this depend on x86 is probably not right. It's really whether we have or don't have a certain restriction on how memory accesses are handled, and x86 just happens to be where it's needed, right? Moving this out of the preprocessor would be great. Sometimes it's really annoying to do that, but in the long run it's a good idea. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/908/#review1659 ----------------------------------------------------------- On 2011-11-15 07:00:31, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/908/ > ----------------------------------------------------------- > > (Updated 2011-11-15 07:00:31) > > > Review request for Default. > > > Summary > ------- > > O3 LSQ: Implement TSO > This patch makes O3's LSQ maintain total order between stores. Essentially > only the store at the head of the store buffer is allowed to be in flight. > Only after that store completes, the next store is issued to the memory > system. > > > Diffs > ----- > > src/cpu/o3/lsq_unit.hh e66a566f2cfa > src/cpu/o3/lsq_unit_impl.hh e66a566f2cfa > > Diff: http://reviews.m5sim.org/r/908/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
