> On 2011-11-18 15:35:26, Brad Beckmann wrote: > >
Brad, all the comments below have been addressed in the latest version of the patch. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/894/#review1666 ----------------------------------------------------------- On 2011-11-18 15:50:36, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/894/ > ----------------------------------------------------------- > > (Updated 2011-11-18 15:50:36) > > > Review request for Default. > > > Summary > ------- > > O3, Ruby: Forward invalidations from Ruby to O3 CPU > This patch implements the functionality for forwarding invalidations and > replacements from the L1 cache of the Ruby memory system to the O3 CPU. The > implementation adds a list of ports to RubyPort. Whenever a replacement or an > invalidation is performed, the L1 cache forwards this to all the ports, which > is the LSQ in case of the O3 CPU. > > A couple of issues that need discussion -- > > * How to avoid deadlock in the O3 CPU? The CPU may not be able to proceed if a > particularly cache block is repeatedly invalidated before the CPU can retire > the actual load/store instruction. How can the O3 CPU ensure that at least one > instruction is retired between successive evictions? > > * How to test this implementation? Can the O3 CPU execute from a trace of > instructions? I have an implementation of the TSOTool. I think we can > implement some of the tests that we regularly come across in papers on > consistency models, and those present in manuals from AMD and Intel. > > > Diffs > ----- > > configs/example/se.py 330f8109b199 > configs/ruby/MESI_CMP_directory.py 330f8109b199 > configs/ruby/MI_example.py 330f8109b199 > configs/ruby/MOESI_CMP_directory.py 330f8109b199 > configs/ruby/MOESI_CMP_token.py 330f8109b199 > configs/ruby/MOESI_hammer.py 330f8109b199 > src/mem/protocol/MESI_CMP_directory-L1cache.sm 330f8109b199 > src/mem/protocol/MI_example-cache.sm 330f8109b199 > src/mem/protocol/MOESI_CMP_directory-L1cache.sm 330f8109b199 > src/mem/protocol/MOESI_CMP_token-L1cache.sm 330f8109b199 > src/mem/protocol/MOESI_hammer-cache.sm 330f8109b199 > src/mem/protocol/RubySlicc_Types.sm 330f8109b199 > src/mem/ruby/system/RubyPort.hh 330f8109b199 > src/mem/ruby/system/RubyPort.cc 330f8109b199 > src/mem/ruby/system/Sequencer.hh 330f8109b199 > src/mem/ruby/system/Sequencer.cc 330f8109b199 > > Diff: http://reviews.m5sim.org/r/894/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
