If it doesn’t impact the lsq design much, would prefer a new command so that the code is more clear. At the very least, there should be a comment better explaining what is going on and what makes the packet a snoop packet.
Brad From: Nilay Vaish [mailto:[email protected]] Sent: Friday, January 06, 2012 7:12 PM To: Nilay Vaish; Beckmann, Brad; Default Subject: Re: Review Request: O3, Ruby: Forward invalidations from Ruby to O3 CPU This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/894/ On January 6th, 2012, 4:59 p.m., Brad Beckmann wrote: src/mem/ruby/system/RubyPort.cc<http://reviews.m5sim.org/r/894/diff/8/?file=16993#file16993line699> (Diff revision 8) RubyPort::ruby_eviction_callback(const Address& address) 699 Packet *pkt = new Packet(&req, MemCmd::ReadExReq, -1); Should this use a different MemCmd then ReadExReq? The current code in cache_impl.hh reads the command from the packet the cache just snooped upon and creates a snoop packet with the same command. This snoop packet is received by the lsq. In case of a ReadExReq, the cache will send a snoop packet to the lsq. Hence, I chose this command. I did not find any thing better in packet.cc, unless we want to define a new command. - Nilay On January 4th, 2012, 1:11 p.m., Nilay Vaish wrote: Review request for Default. By Nilay Vaish. Updated 2012-01-04 13:11:44 Description O3, Ruby: Forward invalidations from Ruby to O3 CPU This patch implements the functionality for forwarding invalidations and replacements from the L1 cache of the Ruby memory system to the O3 CPU. The implementation adds a list of ports to RubyPort. Whenever a replacement or an invalidation is performed, the L1 cache forwards this to all the ports, which is the LSQ in case of the O3 CPU. Diffs * configs/ruby/MESI_CMP_directory.py (09b482ee9ae0) * configs/ruby/MI_example.py (09b482ee9ae0) * configs/ruby/MOESI_CMP_directory.py (09b482ee9ae0) * configs/ruby/MOESI_CMP_token.py (09b482ee9ae0) * configs/ruby/MOESI_hammer.py (09b482ee9ae0) * src/mem/protocol/MESI_CMP_directory-L1cache.sm (09b482ee9ae0) * src/mem/protocol/MI_example-cache.sm (09b482ee9ae0) * src/mem/protocol/MOESI_CMP_directory-L1cache.sm (09b482ee9ae0) * src/mem/protocol/MOESI_CMP_token-L1cache.sm (09b482ee9ae0) * src/mem/protocol/MOESI_hammer-cache.sm (09b482ee9ae0) * src/mem/protocol/RubySlicc_Types.sm (09b482ee9ae0) * src/mem/ruby/system/RubyPort.hh (09b482ee9ae0) * src/mem/ruby/system/RubyPort.cc (09b482ee9ae0) * src/mem/ruby/system/Sequencer.hh (09b482ee9ae0) * src/mem/ruby/system/Sequencer.cc (09b482ee9ae0) View Diff<http://reviews.m5sim.org/r/894/diff/> _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
