> On 2012-01-06 16:59:56, Brad Beckmann wrote: > > src/mem/ruby/system/RubyPort.cc, line 699 > > <http://reviews.m5sim.org/r/894/diff/8/?file=16993#file16993line699> > > > > Should this use a different MemCmd then ReadExReq?
The current code in cache_impl.hh reads the command from the packet the cache just snooped upon and creates a snoop packet with the same command. This snoop packet is received by the lsq. In case of a ReadExReq, the cache will send a snoop packet to the lsq. Hence, I chose this command. I did not find any thing better in packet.cc, unless we want to define a new command. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/894/#review1862 ----------------------------------------------------------- On 2012-01-04 13:11:44, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/894/ > ----------------------------------------------------------- > > (Updated 2012-01-04 13:11:44) > > > Review request for Default. > > > Summary > ------- > > O3, Ruby: Forward invalidations from Ruby to O3 CPU > This patch implements the functionality for forwarding invalidations and > replacements from the L1 cache of the Ruby memory system to the O3 CPU. The > implementation adds a list of ports to RubyPort. Whenever a replacement or an > invalidation is performed, the L1 cache forwards this to all the ports, which > is the LSQ in case of the O3 CPU. > > > Diffs > ----- > > configs/ruby/MESI_CMP_directory.py 09b482ee9ae0 > configs/ruby/MI_example.py 09b482ee9ae0 > configs/ruby/MOESI_CMP_directory.py 09b482ee9ae0 > configs/ruby/MOESI_CMP_token.py 09b482ee9ae0 > configs/ruby/MOESI_hammer.py 09b482ee9ae0 > src/mem/protocol/MESI_CMP_directory-L1cache.sm 09b482ee9ae0 > src/mem/protocol/MI_example-cache.sm 09b482ee9ae0 > src/mem/protocol/MOESI_CMP_directory-L1cache.sm 09b482ee9ae0 > src/mem/protocol/MOESI_CMP_token-L1cache.sm 09b482ee9ae0 > src/mem/protocol/MOESI_hammer-cache.sm 09b482ee9ae0 > src/mem/protocol/RubySlicc_Types.sm 09b482ee9ae0 > src/mem/ruby/system/RubyPort.hh 09b482ee9ae0 > src/mem/ruby/system/RubyPort.cc 09b482ee9ae0 > src/mem/ruby/system/Sequencer.hh 09b482ee9ae0 > src/mem/ruby/system/Sequencer.cc 09b482ee9ae0 > > Diff: http://reviews.m5sim.org/r/894/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
