> On 2011-12-03 12:57:30, Steve Reinhardt wrote: > > src/cpu/DummyChecker.py, line 1 > > <http://reviews.m5sim.org/r/910/diff/2/?file=15591#file15591line1> > > > > What's this DummyChecker object for? > > Geoffrey Blake wrote: > In short, the DummyChecker allows checkpoints and fast forwarding to work > by setting up the ports the real checker will need when it is switched in > with the detailed model. > > Steve Reinhardt wrote: > Can you explain in a little more detail why this is needed? What happens > when you try and restore a checkpoint to a system with a checker when you > don't have a DummyChecker in there to begin with?
There needs to be two checker objects (a dummy and the O3Checker) for the ports to be constructed and connected properly. If the dummy is not there the python code errors out stating there are ports that do not exist. On the call to takeOverFrom(), the dummy is then used to transfer its ports to the actual Checker. I just checked if I could use the O3Checker object in place of the dummy and it does work (eliminating the extra files and code). But I do not know how desirable it is for O3 cpu code to be present in the simple cpu code tree. - Geoffrey ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/910/#review1720 ----------------------------------------------------------- On 2011-11-28 10:07:14, Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/910/ > ----------------------------------------------------------- > > (Updated 2011-11-28 10:07:14) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 > > Brings the CheckerCPU back to a functioning state allowing FS and SE mode > checking of the O3CPU. These changes have only been tested with the > ARM ISA. Other ISAs will potentially require modification. > > > Diffs > ----- > > build_opts/ARM_wCHECKER_FS PRE-CREATION > build_opts/ARM_wCHECKER_SE PRE-CREATION > src/arch/arm/isa.cc 62dee0c98d53 > src/arch/arm/isa/insts/m5ops.isa 62dee0c98d53 > src/arch/arm/isa/insts/misc.isa 62dee0c98d53 > src/arch/arm/table_walker.hh 62dee0c98d53 > src/arch/arm/table_walker.cc 62dee0c98d53 > src/arch/arm/tlb.hh 62dee0c98d53 > src/arch/arm/tlb.cc 62dee0c98d53 > src/arch/arm/utility.cc 62dee0c98d53 > src/cpu/BaseCPU.py 62dee0c98d53 > src/cpu/CheckerCPU.py 62dee0c98d53 > src/cpu/DummyChecker.py PRE-CREATION > src/cpu/SConscript 62dee0c98d53 > src/cpu/base.cc 62dee0c98d53 > src/cpu/base_dyn_inst.hh 62dee0c98d53 > src/cpu/base_dyn_inst_impl.hh 62dee0c98d53 > src/cpu/checker/cpu.hh 62dee0c98d53 > src/cpu/checker/cpu.cc 62dee0c98d53 > src/cpu/checker/cpu_impl.hh 62dee0c98d53 > src/cpu/checker/thread_context.hh 62dee0c98d53 > src/cpu/dummy_checker_builder.cc PRE-CREATION > src/cpu/o3/O3CPU.py 62dee0c98d53 > src/cpu/o3/O3Checker.py 62dee0c98d53 > src/cpu/o3/checker_builder.cc 62dee0c98d53 > src/cpu/o3/commit_impl.hh 62dee0c98d53 > src/cpu/o3/cpu.hh 62dee0c98d53 > src/cpu/o3/cpu.cc 62dee0c98d53 > src/cpu/o3/dyn_inst_impl.hh 62dee0c98d53 > src/cpu/o3/fetch_impl.hh 62dee0c98d53 > src/cpu/o3/iew_impl.hh 62dee0c98d53 > src/cpu/o3/lsq_unit_impl.hh 62dee0c98d53 > src/cpu/o3/thread_context.hh 62dee0c98d53 > src/cpu/o3/thread_context_impl.hh 62dee0c98d53 > src/cpu/simple/BaseSimpleCPU.py 62dee0c98d53 > src/cpu/simple/base.hh 62dee0c98d53 > src/cpu/simple/base.cc 62dee0c98d53 > src/cpu/simple_thread.hh 62dee0c98d53 > src/cpu/thread_context.hh 62dee0c98d53 > src/mem/bus.cc 62dee0c98d53 > > Diff: http://reviews.m5sim.org/r/910/diff > > > Testing > ------- > > Successfully runs gzip in SE mode. Successfully boots linux kernel in FS > mode. Works with checkpoints and fast-forwarding. Testing with buggy O3CPUs > to test checker's capabilities. > > > Thanks, > > Geoffrey > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
