> On 2011-12-03 12:57:30, Steve Reinhardt wrote: > > src/cpu/DummyChecker.py, line 1 > > <http://reviews.m5sim.org/r/910/diff/2/?file=15591#file15591line1> > > > > What's this DummyChecker object for? > > Geoffrey Blake wrote: > In short, the DummyChecker allows checkpoints and fast forwarding to work > by setting up the ports the real checker will need when it is switched in > with the detailed model. > > Steve Reinhardt wrote: > Can you explain in a little more detail why this is needed? What happens > when you try and restore a checkpoint to a system with a checker when you > don't have a DummyChecker in there to begin with? > > Geoffrey Blake wrote: > There needs to be two checker objects (a dummy and the O3Checker) for the > ports to be constructed and connected properly. If the dummy is not there the > python code errors out stating there are ports that do not exist. On the > call to takeOverFrom(), the dummy is then used to transfer its ports to the > actual Checker. > > I just checked if I could use the O3Checker object in place of the dummy > and it does work (eliminating the extra files and code). But I do not know > how desirable it is for O3 cpu code to be present in the simple cpu code tree. > > Steve Reinhardt wrote: > This seems pretty hokey to me... I'd think the answer would be to fix the > switchover process to make it more robust rather than to add this mechanism > with the DummyChecker or wedge O3Checker into the SimpleCPU code. In > addition to the general undesirability of having this new object, I'd think > that from a practical perspective you'd like to allow people to use the > checker on checkpointed runs even when they didn't plan ahead and have a > DummyChecker inserted into the original config. > > Is there a way we can create these ports on the fly when they don't > exist? How does this relate to Andreas's single system-wide ProxyPort > change; would that make this problem go away? > > Sorry I forgot to send this comment sooner... I've been meaning to look > into this myself but haven't had the time. > > Andreas Hansson wrote: > I believe the port proxy patch will indeed make this issue go away as the > checker does not have ports on its own (it merely uses existing ports through > proxies).
If ports could be created on the fly, that would eliminate the need for this object. I guess I wasn't totally clear on the DummyChecker. It does not need to be present when taking a checkpoint. It only needs to be present when loading from a checkpoint so all the ports get created correctly at the start of simulation. The checker does have some ports of its own, like the ports to its own TLBs that shadow the CPU object being Checked. But it does piggy back on the CPU's icache and dcache ports. Not sure how that will all fit into the upcoming changes. - Geoffrey ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/910/#review1720 ----------------------------------------------------------- On 2011-12-13 13:25:24, Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/910/ > ----------------------------------------------------------- > > (Updated 2011-12-13 13:25:24) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 > > Brings the CheckerCPU back to a functioning state allowing FS and SE mode > checking of the O3CPU. These changes have only been tested with the > ARM ISA. Other ISAs will potentially require modification. > > > Diffs > ----- > > configs/common/FSConfig.py c1ab57ea8805 > src/arch/arm/isa.cc c1ab57ea8805 > src/arch/arm/isa/insts/m5ops.isa c1ab57ea8805 > src/arch/arm/isa/insts/misc.isa c1ab57ea8805 > src/arch/arm/table_walker.hh c1ab57ea8805 > src/arch/arm/table_walker.cc c1ab57ea8805 > src/arch/arm/tlb.hh c1ab57ea8805 > src/arch/arm/tlb.cc c1ab57ea8805 > src/arch/arm/utility.cc c1ab57ea8805 > src/cpu/BaseCPU.py c1ab57ea8805 > src/cpu/CheckerCPU.py c1ab57ea8805 > src/cpu/DummyChecker.py PRE-CREATION > src/cpu/SConscript c1ab57ea8805 > src/cpu/base.cc c1ab57ea8805 > src/cpu/base_dyn_inst.hh c1ab57ea8805 > src/cpu/base_dyn_inst_impl.hh c1ab57ea8805 > src/cpu/checker/cpu.hh c1ab57ea8805 > src/cpu/checker/cpu.cc c1ab57ea8805 > src/cpu/checker/cpu_impl.hh c1ab57ea8805 > src/cpu/checker/thread_context.hh c1ab57ea8805 > src/cpu/dummy_checker_builder.cc PRE-CREATION > src/cpu/o3/O3CPU.py c1ab57ea8805 > src/cpu/o3/O3Checker.py c1ab57ea8805 > src/cpu/o3/checker_builder.cc c1ab57ea8805 > src/cpu/o3/commit_impl.hh c1ab57ea8805 > src/cpu/o3/cpu.hh c1ab57ea8805 > src/cpu/o3/cpu.cc c1ab57ea8805 > src/cpu/o3/dyn_inst_impl.hh c1ab57ea8805 > src/cpu/o3/fetch_impl.hh c1ab57ea8805 > src/cpu/o3/iew_impl.hh c1ab57ea8805 > src/cpu/o3/lsq_unit_impl.hh c1ab57ea8805 > src/cpu/o3/thread_context.hh c1ab57ea8805 > src/cpu/o3/thread_context_impl.hh c1ab57ea8805 > src/cpu/simple/BaseSimpleCPU.py c1ab57ea8805 > src/cpu/simple/base.hh c1ab57ea8805 > src/cpu/simple/base.cc c1ab57ea8805 > src/cpu/simple_thread.hh c1ab57ea8805 > src/cpu/thread_context.hh c1ab57ea8805 > src/dev/Device.py c1ab57ea8805 > src/dev/isa_fake.hh c1ab57ea8805 > src/dev/isa_fake.cc c1ab57ea8805 > > Diff: http://reviews.m5sim.org/r/910/diff > > > Testing > ------- > > Successfully runs gzip in SE mode. Successfully boots linux kernel in FS > mode. Works with checkpoints and fast-forwarding. Testing with buggy O3CPUs > to test checker's capabilities. > > > Thanks, > > Geoffrey > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
