----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/910/ -----------------------------------------------------------
(Updated 2011-12-13 13:25:24.163979) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 Brings the CheckerCPU back to a functioning state allowing FS and SE mode checking of the O3CPU. These changes have only been tested with the ARM ISA. Other ISAs will potentially require modification. Diffs (updated) ----- configs/common/FSConfig.py c1ab57ea8805 src/arch/arm/isa.cc c1ab57ea8805 src/arch/arm/isa/insts/m5ops.isa c1ab57ea8805 src/arch/arm/isa/insts/misc.isa c1ab57ea8805 src/arch/arm/table_walker.hh c1ab57ea8805 src/arch/arm/table_walker.cc c1ab57ea8805 src/arch/arm/tlb.hh c1ab57ea8805 src/arch/arm/tlb.cc c1ab57ea8805 src/arch/arm/utility.cc c1ab57ea8805 src/cpu/BaseCPU.py c1ab57ea8805 src/cpu/CheckerCPU.py c1ab57ea8805 src/cpu/DummyChecker.py PRE-CREATION src/cpu/SConscript c1ab57ea8805 src/cpu/base.cc c1ab57ea8805 src/cpu/base_dyn_inst.hh c1ab57ea8805 src/cpu/base_dyn_inst_impl.hh c1ab57ea8805 src/cpu/checker/cpu.hh c1ab57ea8805 src/cpu/checker/cpu.cc c1ab57ea8805 src/cpu/checker/cpu_impl.hh c1ab57ea8805 src/cpu/checker/thread_context.hh c1ab57ea8805 src/cpu/dummy_checker_builder.cc PRE-CREATION src/cpu/o3/O3CPU.py c1ab57ea8805 src/cpu/o3/O3Checker.py c1ab57ea8805 src/cpu/o3/checker_builder.cc c1ab57ea8805 src/cpu/o3/commit_impl.hh c1ab57ea8805 src/cpu/o3/cpu.hh c1ab57ea8805 src/cpu/o3/cpu.cc c1ab57ea8805 src/cpu/o3/dyn_inst_impl.hh c1ab57ea8805 src/cpu/o3/fetch_impl.hh c1ab57ea8805 src/cpu/o3/iew_impl.hh c1ab57ea8805 src/cpu/o3/lsq_unit_impl.hh c1ab57ea8805 src/cpu/o3/thread_context.hh c1ab57ea8805 src/cpu/o3/thread_context_impl.hh c1ab57ea8805 src/cpu/simple/BaseSimpleCPU.py c1ab57ea8805 src/cpu/simple/base.hh c1ab57ea8805 src/cpu/simple/base.cc c1ab57ea8805 src/cpu/simple_thread.hh c1ab57ea8805 src/cpu/thread_context.hh c1ab57ea8805 src/dev/Device.py c1ab57ea8805 src/dev/isa_fake.hh c1ab57ea8805 src/dev/isa_fake.cc c1ab57ea8805 Diff: http://reviews.m5sim.org/r/910/diff Testing ------- Successfully runs gzip in SE mode. Successfully boots linux kernel in FS mode. Works with checkpoints and fast-forwarding. Testing with buggy O3CPUs to test checker's capabilities. Thanks, Geoffrey _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
