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Review request for Default. Summary ------- O3 CPU: Remove interruptPending from fetch The fetch stage currently has a variable for tracking whether interrupts are pending are not. This variable's value is communicated from the commit stage. Instead, the variable is being moved to the O3CPU class and will accessed using the pointer to the CPU. Diffs ----- src/cpu/o3/comm.hh ca98021c3f96 src/cpu/o3/commit_impl.hh ca98021c3f96 src/cpu/o3/cpu.hh ca98021c3f96 src/cpu/o3/cpu.cc ca98021c3f96 src/cpu/o3/fetch.hh ca98021c3f96 src/cpu/o3/fetch_impl.hh ca98021c3f96 Diff: http://reviews.m5sim.org/r/960/diff Testing ------- Thanks, Nilay _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
