Hi Nilay, I don't know for sure, but I would guess that there would be a delay. Steve?
I still don't think the issue with the clearInterrupt and pendingInterrupt variables being ever set to false has been addressed. Thanks, Ali On Jan 1, 2012, at 8:09 PM, Nilay Vaish wrote: > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/960/ > > On January 1st, 2012, 4:51 p.m., Ali Saidi wrote: > > I've got a couple of issues with this change. The first is to do with the > general direction. You're solving the problem here by removing the > communication delay from the interrupt pending signal to the processing of > the interrupt. In CPUs there really is a delay for this to propagate, so it's > not clear to me that we want to get rid of it. Furthermore, once the > variables you've added are set, I don't see a way for them to be cleared. > With the previous code the time buffers clear them, but with the new code > they're only ever set, so it seems like this couldn't work. Finally, your > commit message needs to have information about when this problem shows up, > how you addressed it, and what you believe is now fixed. > > Thanks, > Ali > Ali, is there a particular reason that the commit stage of processor > would transmit this information of pending interrupt to the fetch > stage? I admit I don't know how this is done in a processor. Is there > not a common line which any stage can read from, and not that a > particular stage informs others that an interrupt is pending? > > In case of clear interrupt, I agree with you that there should > be a delay between the processing of the interrupt and this > information being received by the fetch stage. > > - Nilay > > > On December 30th, 2011, 4:31 p.m., Nilay Vaish wrote: > > Review request for Default. > By Nilay Vaish. > Updated 2011-12-30 16:31:40 > > Description > > O3 CPU: Remove interruptPending from fetch > The fetch stage currently has a variable for tracking whether interrupts > are pending are not. This variable's value is communicated from the commit > stage. Instead, the variable is being moved to the O3CPU class and will > accessed using the pointer to the CPU. > Diffs > > src/cpu/o3/comm.hh (ca98021c3f96) > src/cpu/o3/commit_impl.hh (ca98021c3f96) > src/cpu/o3/cpu.hh (ca98021c3f96) > src/cpu/o3/cpu.cc (ca98021c3f96) > src/cpu/o3/fetch.hh (ca98021c3f96) > src/cpu/o3/fetch_impl.hh (ca98021c3f96) > View Diff > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
