----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/960/#review1792 -----------------------------------------------------------
I've got a couple of issues with this change. The first is to do with the general direction. You're solving the problem here by removing the communication delay from the interrupt pending signal to the processing of the interrupt. In CPUs there really is a delay for this to propagate, so it's not clear to me that we want to get rid of it. Furthermore, once the variables you've added are set, I don't see a way for them to be cleared. With the previous code the time buffers clear them, but with the new code they're only ever set, so it seems like this couldn't work. Finally, your commit message needs to have information about when this problem shows up, how you addressed it, and what you believe is now fixed. Thanks, Ali src/cpu/o3/commit_impl.hh <http://reviews.m5sim.org/r/960/#comment2328> It's not clear how this would ever be cleared after it's initially set. src/cpu/o3/commit_impl.hh <http://reviews.m5sim.org/r/960/#comment2327> It's not clear to me how this would ever be cleared after it was initially set src/cpu/o3/cpu.hh <http://reviews.m5sim.org/r/960/#comment2325> These aren't doxygen comments. src/cpu/o3/fetch.hh <http://reviews.m5sim.org/r/960/#comment2326> I don't know that you would need clearInterrupt at all if you implemented the code like this. - Ali On 2011-12-30 16:31:40, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/960/ > ----------------------------------------------------------- > > (Updated 2011-12-30 16:31:40) > > > Review request for Default. > > > Summary > ------- > > O3 CPU: Remove interruptPending from fetch > The fetch stage currently has a variable for tracking whether interrupts > are pending are not. This variable's value is communicated from the commit > stage. Instead, the variable is being moved to the O3CPU class and will > accessed using the pointer to the CPU. > > > Diffs > ----- > > src/cpu/o3/comm.hh ca98021c3f96 > src/cpu/o3/commit_impl.hh ca98021c3f96 > src/cpu/o3/cpu.hh ca98021c3f96 > src/cpu/o3/cpu.cc ca98021c3f96 > src/cpu/o3/fetch.hh ca98021c3f96 > src/cpu/o3/fetch_impl.hh ca98021c3f96 > > Diff: http://reviews.m5sim.org/r/960/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
