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(Updated 2012-01-07 08:11:56.410920) Review request for Default. Summary ------- O3 LSQ: Implement TSO This patch makes O3's LSQ maintain total order between stores. Essentially only the store at the head of the store buffer is allowed to be in flight. Only after that store completes, the next store is issued to the memory system. Diffs (updated) ----- src/arch/alpha/isa_traits.hh 93c6317af258 src/arch/arm/isa_traits.hh 93c6317af258 src/arch/mips/isa_traits.hh 93c6317af258 src/arch/power/isa_traits.hh 93c6317af258 src/arch/sparc/isa_traits.hh 93c6317af258 src/arch/x86/isa_traits.hh 93c6317af258 src/cpu/o3/lsq_unit.hh 93c6317af258 src/cpu/o3/lsq_unit_impl.hh 93c6317af258 Diff: http://reviews.m5sim.org/r/908/diff Testing ------- Thanks, Nilay _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
