If there is a way to enable TSO as a combination of a CPU parameter and ISA characteristic, that would probably be best. However, it doesn’t make sense to me to have it be exclusively a CPU parameter, unless the ARM folks aren’t planning to take advantage of their weaker model when simulating with the O3 model.
Brad From: Korey Sewell [mailto:[email protected]] Sent: Monday, January 09, 2012 11:41 AM To: Nilay Vaish; Beckmann, Brad; Korey Sewell; Default Subject: Re: Review Request: O3 LSQ: Implement TSO This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/908/ Brad, would you be against enabling TSO through a CPU parameter option rather then an ISA characteristic? - Korey On January 7th, 2012, 8:11 a.m., Nilay Vaish wrote: Review request for Default. By Nilay Vaish. Updated 2012-01-07 08:11:56 Description O3 LSQ: Implement TSO This patch makes O3's LSQ maintain total order between stores. Essentially only the store at the head of the store buffer is allowed to be in flight. Only after that store completes, the next store is issued to the memory system. Diffs * src/arch/alpha/isa_traits.hh (93c6317af258) * src/arch/arm/isa_traits.hh (93c6317af258) * src/arch/mips/isa_traits.hh (93c6317af258) * src/arch/power/isa_traits.hh (93c6317af258) * src/arch/sparc/isa_traits.hh (93c6317af258) * src/arch/x86/isa_traits.hh (93c6317af258) * src/cpu/o3/lsq_unit.hh (93c6317af258) * src/cpu/o3/lsq_unit_impl.hh (93c6317af258) View Diff<http://reviews.m5sim.org/r/908/diff/> _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
