> On 2012-01-09 11:38:49, Brad Beckmann wrote: > >
Brad, would you be against enabling TSO through a CPU parameter option rather then an ISA characteristic? - Korey ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/908/#review1870 ----------------------------------------------------------- On 2012-01-07 08:11:56, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/908/ > ----------------------------------------------------------- > > (Updated 2012-01-07 08:11:56) > > > Review request for Default. > > > Summary > ------- > > O3 LSQ: Implement TSO > This patch makes O3's LSQ maintain total order between stores. Essentially > only the store at the head of the store buffer is allowed to be in flight. > Only after that store completes, the next store is issued to the memory > system. > > > Diffs > ----- > > src/arch/alpha/isa_traits.hh 93c6317af258 > src/arch/arm/isa_traits.hh 93c6317af258 > src/arch/mips/isa_traits.hh 93c6317af258 > src/arch/power/isa_traits.hh 93c6317af258 > src/arch/sparc/isa_traits.hh 93c6317af258 > src/arch/x86/isa_traits.hh 93c6317af258 > src/cpu/o3/lsq_unit.hh 93c6317af258 > src/cpu/o3/lsq_unit_impl.hh 93c6317af258 > > Diff: http://reviews.m5sim.org/r/908/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
