> On 2012-01-11 10:42:36, Korey Sewell wrote: > > src/cpu/inorder/cpu.cc, line 646 > > <http://reviews.m5sim.org/r/982/diff/2/?file=20361#file20361line646> > > > > Is "Operations" the right word here? It seems ambiguous. > > > > Assuming that numSimulatedInstructions means macro-ops, I think the > > next derivative of that should mean "numSimulatedMicroOps". > > > > Although the comment clarifies this, operations sounds more like the > > number of Functional Unit *operations* then micro-ops in my opinion. > > Ali Saidi wrote: > I like operations, but I think it's open to debate. macro-ops and > micro-ops are a bit weird. Is an instruction that isn't (cracked, > micro-coded, whatever) a macro-op or a micro-op? > > I think instructions should be whatever is derived from a "word" of > machine code be it 1 or N instruction and then there needs to be something > that is everything that has execute() called on it. This isn't really > micro-ops, because you could have a signal instruction that isn't a micro-op, > but it should count toward the total. ops or operations makes sense to me > here. > > > > > > Korey Sewell wrote: > Ali, > I'm assuming that a single instruction gets counted as one operation so > that the number of operations is always >= the number of instructions. Does > that make sense? > > To try to be clearer, if you had this instruction trace: > <start macro-op sn:1> > <micro-op 1> > <micro-op 2> > <micro-op 3> > <end macro-op sn:1> > signal instruction > <start macro-op sn:2> > <micro-op 1> > <micro-op 2> > <micro-op 3> > <end macro-op sn:2> > > Then your stats would look like: > totalInstructions: 3 > totalOps/Operations:7 > > Would you agree on that stat count? > > Using micro-op for an instruction that isn't "cracked" is fuzzy and > probably just wrong so I see your contention there. > > Gabe Black wrote: > Sequence numbers (sn:xxx) are assigned to the StaticInsts that make it > down the pipe, so macroops don't have them at all and microops (and regular > instructions, and speculatively executed instances of each) would each have a > unique one.
Ahhh, I see. I think this is an issue that I was ran into with the InOrder CPU and microps where I wanted each micro-op to have a separate sub number off the micro-op such as: <macro-op sn:1 micro-op 1> <macro-op sn:1 micro-op 2> <macro-op sn:2 micro-op 3> <signal instruction sn:2> etc. That makes sense to me but that's not how it's done in any of the models so it's up to me to conform there :) As for my running example of how stats would look like, I'd like to give it another pass. The trace would be this: <start macro-op> micro-op sn:1 micro-op sn:2 micro-op sn:3 <end macro-op> signal instruction sn:4 <start macro-op> micro-op sn:5 micro-op sn:6 micro-op sn:7 <end macro-op> Would the stats be this (call it A): ops:7 insts: 3 (counting a whole macro-op as an instruction) or this (call it B): ops: 7 insts:1 - Korey ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/982/#review1906 ----------------------------------------------------------- On 2012-01-10 08:47:41, Anthony Gutierrez wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/982/ > ----------------------------------------------------------- > > (Updated 2012-01-10 08:47:41) > > > Review request for Default. > > > Summary > ------- > > Changeset 8650:2b39160c9a96 > --------------------------- > [mq]: bug.patch > > > Diffs > ----- > > src/arch/noisa/cpu_dummy.hh UNKNOWN > src/cpu/base.hh UNKNOWN > src/cpu/base.cc UNKNOWN > src/cpu/inorder/cpu.hh UNKNOWN > src/cpu/inorder/cpu.cc UNKNOWN > src/cpu/inorder/inorder_dyn_inst.hh UNKNOWN > src/cpu/o3/commit.hh UNKNOWN > src/cpu/o3/commit_impl.hh UNKNOWN > src/cpu/o3/cpu.hh UNKNOWN > src/cpu/o3/cpu.cc UNKNOWN > src/cpu/simple/base.hh UNKNOWN > src/cpu/simple/base.cc UNKNOWN > src/cpu/thread_state.hh UNKNOWN > src/cpu/thread_state.cc UNKNOWN > src/sim/stat_control.cc UNKNOWN > > Diff: http://reviews.m5sim.org/r/982/diff > > > Testing > ------- > > > Thanks, > > Anthony > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
