changeset 0909f8ed7aa0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0909f8ed7aa0
description:
Merge with main repository.
diffstat:
SConstruct |
1 +
configs/common/FSConfig.py |
2 +-
configs/example/ruby_fs.py |
18 +-
configs/ruby/Ruby.py |
10 +-
src/SConscript |
117 +-
src/arch/alpha/ev5.cc |
7 +-
src/arch/alpha/isa/mem.isa |
2 +-
src/arch/alpha/linux/linux.hh |
1 +
src/arch/alpha/process.cc |
2 +-
src/arch/alpha/tru64/tru64.hh |
1 +
src/arch/arm/isa/formats/fp.isa |
18 +-
src/arch/arm/isa/insts/fp.isa |
4 +-
src/arch/arm/isa/insts/macromem.isa |
7 +-
src/arch/arm/isa/insts/neon.isa |
16 +-
src/arch/arm/isa/templates/mem.isa |
4 +-
src/arch/arm/linux/linux.hh |
1 +
src/arch/arm/linux/process.cc |
2 +-
src/arch/arm/process.cc |
3 +-
src/arch/mips/isa/decoder.isa |
8 +-
src/arch/mips/isa/formats/mt.isa |
22 +-
src/arch/mips/isa/includes.isa |
2 +
src/arch/mips/linux/linux.hh |
1 +
src/arch/mips/process.cc |
2 +-
src/arch/mips/tlb.cc |
2 -
src/arch/power/isa/formats/mem.isa |
2 +-
src/arch/power/linux/linux.hh |
1 +
src/arch/power/process.cc |
3 +-
src/arch/power/tlb.cc |
2 -
src/arch/sparc/isa/formats/mem/util.isa |
4 +-
src/arch/sparc/linux/linux.hh |
1 +
src/arch/sparc/process.cc |
3 +-
src/arch/sparc/solaris/solaris.hh |
1 +
src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py |
36 +
src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py |
8 +
src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py |
24 +
src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py |
12 +
src/arch/x86/isa/insts/general_purpose/logical.py |
28 +
src/arch/x86/isa/insts/general_purpose/semaphores.py |
8 +
src/arch/x86/isa/microops/base.isa |
3 +-
src/arch/x86/isa/microops/specop.isa |
53 +
src/arch/x86/linux/linux.hh |
2 +
src/arch/x86/process.cc |
9 +-
src/base/inet.cc |
1 +
src/cpu/base.cc |
3 +-
src/cpu/inorder/cpu.cc |
3 +-
src/cpu/legiontrace.cc |
2 +-
src/cpu/o3/cpu.cc |
1 -
src/cpu/o3/rename_impl.hh |
16 +-
src/cpu/testers/rubytest/Check.hh |
1 -
src/dev/io_device.cc |
28 +
src/dev/io_device.hh |
32 +-
src/dev/mc146818.cc |
2 +-
src/kern/tru64/tru64.hh |
4 +-
src/mem/SConscript |
5 +-
src/mem/cache/tags/iic.cc |
2 -
src/mem/page_table.cc |
45 +-
src/mem/page_table.hh |
23 +-
src/mem/protocol/MESI_CMP_directory-L1cache.sm |
15 +
src/mem/protocol/MESI_CMP_directory-L2cache.sm |
18 +-
src/mem/protocol/MESI_CMP_directory.slicc |
1 -
src/mem/protocol/MI_example.slicc |
1 -
src/mem/protocol/MOESI_CMP_directory.slicc |
1 -
src/mem/protocol/MOESI_CMP_token.slicc |
1 -
src/mem/protocol/MOESI_hammer.slicc |
1 -
src/mem/protocol/RubySlicc_ComponentMapping.sm |
22 -
src/mem/protocol/RubySlicc_Types.sm |
2 +-
src/mem/protocol/standard_1level_CMP-protocol.sm |
40 -
src/mem/protocol/standard_CMP-protocol.sm |
36 -
src/mem/ruby/SConscript |
1 -
src/mem/ruby/common/Address.hh |
3 +-
src/mem/ruby/common/DataBlock.hh |
2 +-
src/mem/ruby/common/Driver.hh |
1 -
src/mem/ruby/common/Global.hh |
11 +-
src/mem/ruby/common/Histogram.hh |
2 +-
src/mem/ruby/common/NetDest.hh |
1 -
src/mem/ruby/common/Set.hh |
1 -
src/mem/ruby/common/TypeDefines.hh |
5 +
src/mem/ruby/eventqueue/RubyEventQueue.hh |
2 +-
src/mem/ruby/network/Network.hh |
1 -
src/mem/ruby/network/Topology.hh |
3 +-
src/mem/ruby/network/fault_model/FaultModel.cc |
278 ++
src/mem/ruby/network/fault_model/FaultModel.hh |
142 +
src/mem/ruby/network/fault_model/FaultModel.py |
302 ++
src/mem/ruby/network/fault_model/SConscript |
43 +
src/mem/ruby/network/garnet/BaseGarnetNetwork.cc |
3 +
src/mem/ruby/network/garnet/BaseGarnetNetwork.hh |
4 +
src/mem/ruby/network/garnet/BaseGarnetNetwork.py |
2 +
src/mem/ruby/network/garnet/NetworkHeader.hh |
3 -
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc |
17 +
src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh |
1 +
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc |
29 +
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh |
12 +
src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh |
1 +
src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh |
1 +
src/mem/ruby/network/orion/Clock.cc |
7 -
src/mem/ruby/network/simple/PerfectSwitch.cc |
3 +-
src/mem/ruby/network/simple/PerfectSwitch.hh |
1 -
src/mem/ruby/network/simple/SimpleNetwork.hh |
1 -
src/mem/ruby/network/simple/Throttle.cc |
4 +-
src/mem/ruby/network/simple/Throttle.hh |
1 -
src/mem/ruby/profiler/AccessTraceForAddress.hh |
1 -
src/mem/ruby/profiler/AddressProfiler.hh |
1 -
src/mem/ruby/profiler/CacheProfiler.hh |
1 -
src/mem/ruby/profiler/MemCntrlProfiler.hh |
2 +-
src/mem/ruby/profiler/Profiler.hh |
1 -
src/mem/ruby/recorder/CacheRecorder.hh |
1 -
src/mem/ruby/recorder/TraceRecord.cc |
8 +-
src/mem/ruby/recorder/TraceRecord.hh |
1 -
src/mem/ruby/recorder/Tracer.hh |
1 -
src/mem/ruby/slicc_interface/Message.hh |
1 +
src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh |
68 -
src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh |
1 -
src/mem/ruby/slicc_interface/RubySlicc_Util.hh |
1 -
src/mem/ruby/system/DMASequencer.cc |
23 +-
src/mem/ruby/system/DMASequencer.hh |
2 +-
src/mem/ruby/system/MachineID.hh |
1 -
src/mem/ruby/system/NodeID.hh |
45 -
src/mem/ruby/system/PersistentTable.hh |
1 +
src/mem/ruby/system/PseudoLRUPolicy.hh |
3 -
src/mem/ruby/system/RubyPort.cc |
72 +-
src/mem/ruby/system/RubyPort.hh |
2 +-
src/mem/ruby/system/Sequencer.cc |
378 +-
src/mem/ruby/system/Sequencer.hh |
17 +-
src/mem/slicc/symbols/StateMachine.py |
2 +-
src/mem/slicc/symbols/Type.py |
53 +-
src/mem/translating_port.cc |
8 +-
src/python/SConscript |
1 +
src/python/m5/SimObject.py |
267 +-
src/python/m5/internal/__init__.py |
1 -
src/python/m5/params.py |
33 +-
src/python/swig/pyobject.cc |
5 -
src/python/swig/pyobject.i |
55 +
src/python/swig/sim_object.i |
81 -
src/python/swig/system.i |
46 -
src/sim/System.py |
11 +-
src/sim/process.cc |
14 +-
src/sim/process.hh |
2 +
src/sim/sim_object_params.hh |
58 -
src/sim/syscall_emul.cc |
3 +-
src/sim/syscall_emul.hh |
55 +-
src/sim/system.cc |
4 +-
src/sim/system.hh |
4 +-
tests/SConscript |
4 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/simout |
9 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt |
668 ++--
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout |
11 +-
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt |
1242 +++++-----
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal |
2 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/simout |
9 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt |
718 ++--
tests/long/20.parser/ref/x86/linux/o3-timing/simout |
9 +-
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt |
714 ++--
tests/long/70.twolf/ref/x86/linux/o3-timing/simout |
11 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt |
708 ++--
tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt |
1048 ++++----
tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt |
1238 ++++----
156 files changed, 5062 insertions(+), 4311 deletions(-)
diffs (truncated from 12991 to 300 lines):
diff -r e2ac2b7164dd -r 0909f8ed7aa0 SConstruct
--- a/SConstruct Fri Nov 18 02:20:22 2011 -0800
+++ b/SConstruct Sat Jan 07 02:10:34 2012 -0800
@@ -487,6 +487,7 @@
# Note CCVERSION doesn't work here because it is run with the CC
# before we override it from the command line
gcc_version = readCommand([main['CXX'], '-dumpversion'], exception=False)
+ main['GCC_VERSION'] = gcc_version
if not compareVersions(gcc_version, '4.4.1') or \
not compareVersions(gcc_version, '4.4.2'):
print 'Info: Tree vectorizer in GCC 4.4.1 & 4.4.2 is buggy, disabling.'
diff -r e2ac2b7164dd -r 0909f8ed7aa0 configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Fri Nov 18 02:20:22 2011 -0800
+++ b/configs/common/FSConfig.py Sat Jan 07 02:10:34 2012 -0800
@@ -253,7 +253,7 @@
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
if mdesc.disk().count('android'):
- boot_flags += "init=/init "
+ boot_flags += " init=/init "
self.boot_osflags = boot_flags
self.physmem.port = self.membus.port
diff -r e2ac2b7164dd -r 0909f8ed7aa0 configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py Fri Nov 18 02:20:22 2011 -0800
+++ b/configs/example/ruby_fs.py Sat Jan 07 02:10:34 2012 -0800
@@ -30,18 +30,18 @@
# Full system configuraiton for ruby
#
+import optparse
import os
-import optparse
import sys
from os.path import join as joinpath
import m5
from m5.defines import buildEnv
from m5.objects import *
-from m5.util import addToPath, panic
+from m5.util import addToPath, fatal
if not buildEnv['FULL_SYSTEM']:
- panic("This script requires full-system mode (*_FS).")
+ fatal("This script requires full-system mode (*_FS).")
addToPath('../common')
addToPath('../ruby')
@@ -60,7 +60,9 @@
m5_root = os.path.dirname(config_root)
parser = optparse.OptionParser()
-
+# System options
+parser.add_option("--kernel", action="store", type="string")
+parser.add_option("--script", action="store", type="string")
# Benchmark options
parser.add_option("-b", "--benchmark", action="store", type="string",
dest="benchmark",
@@ -117,9 +119,15 @@
else:
fatal("incapable of building non-alpha or non-x86 full system!")
+if options.kernel is not None:
+ system.kernel = binary(options.kernel)
+
+if options.script is not None:
+ system.readfile = options.script
+
+system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
Ruby.create_system(options, system, system.piobus, system._dma_devices)
-system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
for (i, cpu) in enumerate(system.cpu):
#
diff -r e2ac2b7164dd -r 0909f8ed7aa0 configs/ruby/Ruby.py
--- a/configs/ruby/Ruby.py Fri Nov 18 02:20:22 2011 -0800
+++ b/configs/ruby/Ruby.py Sat Jan 07 02:10:34 2012 -0800
@@ -40,6 +40,8 @@
help="the number of rows in the mesh topology")
parser.add_option("--garnet-network", type="string", default=None,
help="'fixed'|'flexible'")
+ parser.add_option("--network-fault-model", action="store_true",
default=False,
+ help="enable network fault model: see
src/mem/ruby/network/fault_model/")
# ruby mapping options
parser.add_option("--numa-high-bit", type="int", default=0,
@@ -109,7 +111,13 @@
print "Error: could not create topology %s" % options.topology
raise
- network = NetworkClass(ruby_system = ruby, topology = net_topology)
+ if options.network_fault_model:
+ assert(options.garnet_network == "fixed")
+ fault_model = FaultModel()
+ network = NetworkClass(ruby_system = ruby, topology = net_topology,\
+ enable_fault_model=True, fault_model =
fault_model)
+ else:
+ network = NetworkClass(ruby_system = ruby, topology = net_topology)
#
# Loop through the directory controlers.
diff -r e2ac2b7164dd -r 0909f8ed7aa0 src/SConscript
--- a/src/SConscript Fri Nov 18 02:20:22 2011 -0800
+++ b/src/SConscript Sat Jan 07 02:10:34 2012 -0800
@@ -51,7 +51,7 @@
build_env = [(opt, env[opt]) for opt in export_vars]
-from m5.util import code_formatter
+from m5.util import code_formatter, compareVersions
########################################################################
# Code for adding source files of various types
@@ -449,7 +449,13 @@
sim_objects = m5.SimObject.allClasses
all_enums = m5.params.allEnums
-all_params = {}
+# Find param types that need to be explicitly wrapped with swig.
+# These will be recognized because the ParamDesc will have a
+# swig_decl() method. Most param types are based on types that don't
+# need this, either because they're based on native types (like Int)
+# or because they're SimObjects (which get swigged independently).
+# For now the only things handled here are VectorParam types.
+params_to_swig = {}
for name,obj in sorted(sim_objects.iteritems()):
for param in obj._params.local.values():
# load the ptype attribute now because it depends on the
@@ -461,8 +467,8 @@
if not hasattr(param, 'swig_decl'):
continue
pname = param.ptype_str
- if pname not in all_params:
- all_params[pname] = param
+ if pname not in params_to_swig:
+ params_to_swig[pname] = param
########################################################################
#
@@ -523,24 +529,23 @@
# Create all of the SimObject param headers and enum headers
#
-def createSimObjectParam(target, source, env):
+def createSimObjectParamStruct(target, source, env):
assert len(target) == 1 and len(source) == 1
name = str(source[0].get_contents())
obj = sim_objects[name]
code = code_formatter()
- obj.cxx_decl(code)
+ obj.cxx_param_decl(code)
code.write(target[0].abspath)
-def createSwigParam(target, source, env):
+def createParamSwigWrapper(target, source, env):
assert len(target) == 1 and len(source) == 1
name = str(source[0].get_contents())
- param = all_params[name]
+ param = params_to_swig[name]
code = code_formatter()
- code('%module(package="m5.internal") $0_${name}', param.file_ext)
param.swig_decl(code)
code.write(target[0].abspath)
@@ -554,7 +559,7 @@
obj.cxx_def(code)
code.write(target[0].abspath)
-def createEnumParam(target, source, env):
+def createEnumDecls(target, source, env):
assert len(target) == 1 and len(source) == 1
name = str(source[0].get_contents())
@@ -564,25 +569,25 @@
obj.cxx_decl(code)
code.write(target[0].abspath)
-def createEnumSwig(target, source, env):
+def createEnumSwigWrapper(target, source, env):
assert len(target) == 1 and len(source) == 1
name = str(source[0].get_contents())
obj = all_enums[name]
code = code_formatter()
- code('''\
-%module(package="m5.internal") enum_$name
-
-%{
-#include "enums/$name.hh"
-%}
-
-%include "enums/$name.hh"
-''')
+ obj.swig_decl(code)
code.write(target[0].abspath)
-# Generate all of the SimObject param struct header files
+def createSimObjectSwigWrapper(target, source, env):
+ name = source[0].get_contents()
+ obj = sim_objects[name]
+
+ code = code_formatter()
+ obj.swig_decl(code)
+ code.write(target[0].abspath)
+
+# Generate all of the SimObject param C++ struct header files
params_hh_files = []
for name,simobj in sorted(sim_objects.iteritems()):
py_source = PySource.modules[simobj.__module__]
@@ -591,16 +596,16 @@
hh_file = File('params/%s.hh' % name)
params_hh_files.append(hh_file)
env.Command(hh_file, Value(name),
- MakeAction(createSimObjectParam, Transform("SO PARAM")))
+ MakeAction(createSimObjectParamStruct, Transform("SO PARAM")))
env.Depends(hh_file, depends + extra_deps)
-# Generate any parameter header files needed
+# Generate any needed param SWIG wrapper files
params_i_files = []
-for name,param in all_params.iteritems():
- i_file = File('python/m5/internal/%s_%s.i' % (param.file_ext, name))
+for name,param in params_to_swig.iteritems():
+ i_file = File('python/m5/internal/%s.i' % (param.swig_module_name()))
params_i_files.append(i_file)
env.Command(i_file, Value(name),
- MakeAction(createSwigParam, Transform("SW PARAM")))
+ MakeAction(createParamSwigWrapper, Transform("SW PARAM")))
env.Depends(i_file, depends)
SwigSource('m5.internal', i_file)
@@ -617,54 +622,22 @@
hh_file = File('enums/%s.hh' % name)
env.Command(hh_file, Value(name),
- MakeAction(createEnumParam, Transform("EN PARAM")))
+ MakeAction(createEnumDecls, Transform("ENUMDECL")))
env.Depends(hh_file, depends + extra_deps)
i_file = File('python/m5/internal/enum_%s.i' % name)
env.Command(i_file, Value(name),
- MakeAction(createEnumSwig, Transform("ENUMSWIG")))
+ MakeAction(createEnumSwigWrapper, Transform("ENUMSWIG")))
env.Depends(i_file, depends + extra_deps)
SwigSource('m5.internal', i_file)
-def buildParam(target, source, env):
- name = source[0].get_contents()
- obj = sim_objects[name]
- class_path = obj.cxx_class.split('::')
- classname = class_path[-1]
- namespaces = class_path[:-1]
- params = obj._params.local.values()
-
- code = code_formatter()
-
- code('%module(package="m5.internal") param_$name')
- code()
- code('%{')
- code('#include "params/$obj.hh"')
- for param in params:
- param.cxx_predecls(code)
- code('%}')
- code()
-
- for param in params:
- param.swig_predecls(code)
-
- code()
- if obj._base:
- code('%import "python/m5/internal/param_${{obj._base}}.i"')
- code()
- obj.swig_objdecls(code)
- code()
-
- code('%include "params/$obj.hh"')
-
- code.write(target[0].abspath)
-
+# Generate SimObject SWIG wrapper files
for name in sim_objects.iterkeys():
- params_file = File('python/m5/internal/param_%s.i' % name)
- env.Command(params_file, Value(name),
- MakeAction(buildParam, Transform("BLDPARAM")))
- env.Depends(params_file, depends)
- SwigSource('m5.internal', params_file)
+ i_file = File('python/m5/internal/param_%s.i' % name)
+ env.Command(i_file, Value(name),
+ MakeAction(createSimObjectSwigWrapper, Transform("SO SWIG")))
+ env.Depends(i_file, depends)
+ SwigSource('m5.internal', i_file)
# Generate the main swig init file
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