changeset 8af87554ad7e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8af87554ad7e
description:
Merge with main repository.
diffstat:
configs/example/se.py | 1 -
configs/ruby/Ruby.py | 5 ++++-
src/arch/arm/vtophys.hh | 1 -
src/arch/mips/vtophys.hh | 1 -
src/arch/power/vtophys.hh | 1 -
src/arch/sparc/vtophys.hh | 4 ----
src/cpu/inorder/thread_context.hh | 2 --
src/cpu/o3/thread_context.hh | 2 --
src/cpu/simple_thread.hh | 2 --
src/kern/solaris/solaris.hh | 2 --
src/mem/ruby/system/RubyPort.cc | 3 +--
src/mem/ruby/system/RubyPort.hh | 2 +-
tests/configs/memtest-ruby.py | 4 ----
tests/configs/o3-timing-mp-ruby.py | 2 ++
tests/configs/o3-timing-ruby.py | 3 +++
tests/configs/rubytest-ruby.py | 3 ---
tests/configs/simple-atomic-mp-ruby.py | 2 ++
tests/configs/simple-timing-mp-ruby.py | 3 ---
tests/configs/simple-timing-ruby.py | 3 ---
19 files changed, 13 insertions(+), 33 deletions(-)
diffs (242 lines):
diff -r 35e77c938919 -r 8af87554ad7e configs/example/se.py
--- a/configs/example/se.py Sun Jan 29 03:27:15 2012 -0800
+++ b/configs/example/se.py Mon Jan 30 21:07:57 2012 -0800
@@ -181,7 +181,6 @@
options.use_map = True
Ruby.create_system(options, system)
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
- system.system_port = system.ruby._sys_port_proxy.port
else:
system.system_port = system.membus.port
system.physmem.port = system.membus.port
diff -r 35e77c938919 -r 8af87554ad7e configs/ruby/Ruby.py
--- a/configs/ruby/Ruby.py Sun Jan 29 03:27:15 2012 -0800
+++ b/configs/ruby/Ruby.py Mon Jan 30 21:07:57 2012 -0800
@@ -105,6 +105,10 @@
# full-fledged controller
system.sys_port_proxy = sys_port_proxy
+ # Connect the system port for loading of binaries etc
+ system.system_port = system.sys_port_proxy.port
+
+
#
# Set the network classes based on the command line options
#
@@ -182,5 +186,4 @@
ruby.profiler = ruby_profiler
ruby.mem_size = total_mem_size
ruby._cpu_ruby_ports = cpu_sequencers
- ruby._sys_port_proxy = sys_port_proxy
ruby.random_seed = options.random_seed
diff -r 35e77c938919 -r 8af87554ad7e src/arch/arm/vtophys.hh
--- a/src/arch/arm/vtophys.hh Sun Jan 29 03:27:15 2012 -0800
+++ b/src/arch/arm/vtophys.hh Mon Jan 30 21:07:57 2012 -0800
@@ -38,7 +38,6 @@
#include "arch/arm/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace ArmISA {
inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
diff -r 35e77c938919 -r 8af87554ad7e src/arch/mips/vtophys.hh
--- a/src/arch/mips/vtophys.hh Sun Jan 29 03:27:15 2012 -0800
+++ b/src/arch/mips/vtophys.hh Mon Jan 30 21:07:57 2012 -0800
@@ -38,7 +38,6 @@
#include "arch/mips/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace MipsISA {
Addr vtophys(Addr vaddr);
diff -r 35e77c938919 -r 8af87554ad7e src/arch/power/vtophys.hh
--- a/src/arch/power/vtophys.hh Sun Jan 29 03:27:15 2012 -0800
+++ b/src/arch/power/vtophys.hh Mon Jan 30 21:07:57 2012 -0800
@@ -40,7 +40,6 @@
#include "arch/power/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace PowerISA {
diff -r 35e77c938919 -r 8af87554ad7e src/arch/sparc/vtophys.hh
--- a/src/arch/sparc/vtophys.hh Sun Jan 29 03:27:15 2012 -0800
+++ b/src/arch/sparc/vtophys.hh Mon Jan 30 21:07:57 2012 -0800
@@ -36,13 +36,9 @@
#include "arch/sparc/pagetable.hh"
class ThreadContext;
-class FunctionalPort;
namespace SparcISA {
-PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
-
Addr vtophys(Addr vaddr);
Addr vtophys(ThreadContext *tc, Addr vaddr);
diff -r 35e77c938919 -r 8af87554ad7e src/cpu/inorder/thread_context.hh
--- a/src/cpu/inorder/thread_context.hh Sun Jan 29 03:27:15 2012 -0800
+++ b/src/cpu/inorder/thread_context.hh Mon Jan 30 21:07:57 2012 -0800
@@ -44,8 +44,6 @@
class Statistics;
};
-class TranslatingPort;
-
/**
* Derived ThreadContext class for use with the InOrderCPU. It
* provides the interface for any external objects to access a
diff -r 35e77c938919 -r 8af87554ad7e src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh Sun Jan 29 03:27:15 2012 -0800
+++ b/src/cpu/o3/thread_context.hh Mon Jan 30 21:07:57 2012 -0800
@@ -40,8 +40,6 @@
class Statistics;
};
-class TranslatingPort;
-
/**
* Derived ThreadContext class for use with the O3CPU. It
* provides the interface for any external objects to access a
diff -r 35e77c938919 -r 8af87554ad7e src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh Sun Jan 29 03:27:15 2012 -0800
+++ b/src/cpu/simple_thread.hh Mon Jan 30 21:07:57 2012 -0800
@@ -57,8 +57,6 @@
class FunctionProfile;
class ProfileNode;
-class PhysicalPort;
-class TranslatingPort;
namespace TheISA {
namespace Kernel {
diff -r 35e77c938919 -r 8af87554ad7e src/kern/solaris/solaris.hh
--- a/src/kern/solaris/solaris.hh Sun Jan 29 03:27:15 2012 -0800
+++ b/src/kern/solaris/solaris.hh Mon Jan 30 21:07:57 2012 -0800
@@ -34,8 +34,6 @@
#include "base/types.hh"
#include "kern/operatingsystem.hh"
-class TranslatingPort;
-
///
/// This class encapsulates the types, structures, constants,
/// functions, and syscall-number mappings specific to the Solaris
diff -r 35e77c938919 -r 8af87554ad7e src/mem/ruby/system/RubyPort.cc
--- a/src/mem/ruby/system/RubyPort.cc Sun Jan 29 03:27:15 2012 -0800
+++ b/src/mem/ruby/system/RubyPort.cc Mon Jan 30 21:07:57 2012 -0800
@@ -88,8 +88,7 @@
// RubyPort should only have one port to physical memory
assert (physMemPort == NULL);
- physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this,
- ruby_system, access_phys_mem);
+ physMemPort = new PioPort(csprintf("%s-physMemPort", name()), this);
return physMemPort;
}
diff -r 35e77c938919 -r 8af87554ad7e src/mem/ruby/system/RubyPort.hh
--- a/src/mem/ruby/system/RubyPort.hh Sun Jan 29 03:27:15 2012 -0800
+++ b/src/mem/ruby/system/RubyPort.hh Mon Jan 30 21:07:57 2012 -0800
@@ -155,7 +155,7 @@
uint16_t m_port_id;
uint64_t m_request_cnt;
- M5Port* physMemPort;
+ PioPort* physMemPort;
/*! Vector of CPU Port attached to this Ruby port. */
typedef std::vector<M5Port*>::iterator CpuPortIter;
diff -r 35e77c938919 -r 8af87554ad7e tests/configs/memtest-ruby.py
--- a/tests/configs/memtest-ruby.py Sun Jan 29 03:27:15 2012 -0800
+++ b/tests/configs/memtest-ruby.py Mon Jan 30 21:07:57 2012 -0800
@@ -106,10 +106,6 @@
#
ruby_port.access_phys_mem = False
-
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
diff -r 35e77c938919 -r 8af87554ad7e tests/configs/o3-timing-mp-ruby.py
--- a/tests/configs/o3-timing-mp-ruby.py Sun Jan 29 03:27:15 2012 -0800
+++ b/tests/configs/o3-timing-mp-ruby.py Mon Jan 30 21:07:57 2012 -0800
@@ -46,6 +46,8 @@
# connect memory to membus
system.physmem.port = system.membus.port
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
# -----------------------
# run simulation
diff -r 35e77c938919 -r 8af87554ad7e tests/configs/o3-timing-ruby.py
--- a/tests/configs/o3-timing-ruby.py Sun Jan 29 03:27:15 2012 -0800
+++ b/tests/configs/o3-timing-ruby.py Mon Jan 30 21:07:57 2012 -0800
@@ -43,4 +43,7 @@
system.physmem.port = system.membus.port
cpu.connectAllPorts(system.membus)
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
+
root = Root(full_system = False, system = system)
diff -r 35e77c938919 -r 8af87554ad7e tests/configs/rubytest-ruby.py
--- a/tests/configs/rubytest-ruby.py Sun Jan 29 03:27:15 2012 -0800
+++ b/tests/configs/rubytest-ruby.py Mon Jan 30 21:07:57 2012 -0800
@@ -102,9 +102,6 @@
#
ruby_port.access_phys_mem = False
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
diff -r 35e77c938919 -r 8af87554ad7e tests/configs/simple-atomic-mp-ruby.py
--- a/tests/configs/simple-atomic-mp-ruby.py Sun Jan 29 03:27:15 2012 -0800
+++ b/tests/configs/simple-atomic-mp-ruby.py Mon Jan 30 21:07:57 2012 -0800
@@ -47,6 +47,8 @@
# connect memory to membus
system.physmem.port = system.membus.port
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
# -----------------------
# run simulation
diff -r 35e77c938919 -r 8af87554ad7e tests/configs/simple-timing-mp-ruby.py
--- a/tests/configs/simple-timing-mp-ruby.py Sun Jan 29 03:27:15 2012 -0800
+++ b/tests/configs/simple-timing-mp-ruby.py Mon Jan 30 21:07:57 2012 -0800
@@ -85,9 +85,6 @@
cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
diff -r 35e77c938919 -r 8af87554ad7e tests/configs/simple-timing-ruby.py
--- a/tests/configs/simple-timing-ruby.py Sun Jan 29 03:27:15 2012 -0800
+++ b/tests/configs/simple-timing-ruby.py Mon Jan 30 21:07:57 2012 -0800
@@ -81,9 +81,6 @@
#
cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
# -----------------------
# run simulation
# -----------------------
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