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src/cpu/o3/commit_impl.hh <http://reviews.gem5.org/r/1007/#comment2540> It looks like we already have the DynInstPtr here in the case where the rob is not empty... in fact just looking at this code I'd say that the call to getSquashInst() below will only ever return either NULL or whatever rob->readHeadInst() returns here. Right? src/cpu/o3/fetch_impl.hh <http://reviews.gem5.org/r/1007/#comment2539> This definitely needs a comment that summarizes your response to Ali for posterity. - Steve Reinhardt On Jan. 28, 2012, 9 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1007/ > ----------------------------------------------------------- > > (Updated Jan. 28, 2012, 9 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8731:10a06bd36839 > --------------------------- > O3 CPU: Provide the squashing instruction > This patch adds a function to the ROB that will get the squashing instruction > from the ROB's list of instructions. This squashing instruction is used for > figuring out the macroop from which the fetch stage should fetch the microops. > Further, a check has been added that if the instructions are to be fetched > from the cache maintained by the fetch stage, then the data in the cache > should > be valid and the PC of the thread being fetched from is same as the address of > the cache block. > > > Diffs > ----- > > src/cpu/o3/commit_impl.hh 9d7c1dc54954 > src/cpu/o3/fetch_impl.hh 9d7c1dc54954 > src/cpu/o3/rob.hh 9d7c1dc54954 > src/cpu/o3/rob_impl.hh 9d7c1dc54954 > > Diff: http://reviews.gem5.org/r/1007/diff/diff > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
