> On Feb. 24, 2012, 11:15 a.m., Nilay Vaish wrote:
> > Andreas, is it necessary to generate the interrupts object in case we know
> > that the cpu will take over the object from another cpu later?
I tried the patch, but I still hit the pio port not being connected issue. I
tried the following commandline:
build/X86/gem5.opt configs/example/fs.py --cpu-type=detailed
--kernel=x86_64-vmlinux-2.6.22.9 --caches -F 1000
...
command line: build/X86/gem5.opt configs/example/fs.py --cpu-type=detailed
--kernel=x86_64-vmlinux-2.6.22.9 --caches -F 1000
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
Listening for com_1 connection on port 3456
warn: Reading current count from inactive timer.
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
panic: Pio port of system.switch_cpus.interrupts not connected to anything!
@ cycle 0
[init:build/X86/dev/io_device.cc, line 69]
Memory Usage: 213616 KBytes
Program aborted at cycle 0
Aborted
....
- Ankita
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/1062/#review2204
-----------------------------------------------------------
On Feb. 24, 2012, 10:35 a.m., Andreas Hansson wrote:
>
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1062/
> -----------------------------------------------------------
>
> (Updated Feb. 24, 2012, 10:35 a.m.)
>
>
> Review request for Default.
>
>
> Description
> -------
>
> CPU: Fix switching in of x86 CPU with interrupt and TLB ports
>
> This patch fixes the, currently broken, switching of CPUs for x86 by
> ensuring that the interrupt device does not initialise the ports if
> the CPU is not connected, and also ensures that the TLB walker ports
> of the new CPU are actually connected. To do the latter the getPort of
> the TLB and TLB walker for x86 were added to override the BaseTLB that
> returns NULL.
>
>
> Diffs
> -----
>
> src/arch/alpha/interrupts.hh 241ee47b0dc6
> src/arch/arm/interrupts.hh 241ee47b0dc6
> src/arch/mips/interrupts.hh 241ee47b0dc6
> src/arch/power/interrupts.hh 241ee47b0dc6
> src/arch/sparc/interrupts.hh 241ee47b0dc6
> src/arch/x86/interrupts.hh 241ee47b0dc6
> src/arch/x86/interrupts.cc 241ee47b0dc6
> src/arch/x86/pagetable_walker.hh 241ee47b0dc6
> src/arch/x86/tlb.hh 241ee47b0dc6
> src/arch/x86/tlb.cc 241ee47b0dc6
> src/cpu/base.cc 241ee47b0dc6
>
> Diff: http://reviews.gem5.org/r/1062/diff/diff
>
>
> Testing
> -------
>
> util/regress all passing (disregarding t1000 and eio)
>
>
> Thanks,
>
> Andreas Hansson
>
>
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
