Sorry folks, I've just been caught up with other stuff lately and not had a chance to run quite a few of the patches that are floating around. Hope to get it done today. Thanks for all the help!
On Tue, Feb 28, 2012 at 8:48 AM, Nilay Vaish <[email protected]> wrote: > > > > On Feb. 27, 2012, 7:30 p.m., Ali Saidi wrote: > > > Ship It! > > > > Gabe Black wrote: > > Uh, this really didn't look it was ready to ship. Ankita said it > didn't fix her problem, and Nilay said he was going to write a new version. > > > > Ali Saidi wrote: > > It seems to fix the problem reported for me and we don't know how > long it's going to take to get a improved solution that fixes the > interrupt, tlb, everything else for all the architectures. I'd prefer to > commit this now so the functionality isn't broken in the head and then > un-do it when a more complete fix is available. Thoughts? > > > > Gabe Black wrote: > > If it fixes the problem then sure, that makes sense. I'm curious why > it didn't work for Ankita. > > > > Andreas Hansson wrote: > > I did ask Ankita to re-run everything with the patch as it > definitely solves the problem on my side. Any news on this front, Ankita? > > I have posted two new patches, these combine the patch posted by Andreas > and the one that > Ali emailed me. > > > - Nilay > > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1062/#review2217 > ----------------------------------------------------------- > > > On Feb. 24, 2012, 10:35 a.m., Andreas Hansson wrote: > > > > ----------------------------------------------------------- > > This is an automatically generated e-mail. To reply, visit: > > http://reviews.gem5.org/r/1062/ > > ----------------------------------------------------------- > > > > (Updated Feb. 24, 2012, 10:35 a.m.) > > > > > > Review request for Default. > > > > > > Description > > ------- > > > > CPU: Fix switching in of x86 CPU with interrupt and TLB ports > > > > This patch fixes the, currently broken, switching of CPUs for x86 by > > ensuring that the interrupt device does not initialise the ports if > > the CPU is not connected, and also ensures that the TLB walker ports > > of the new CPU are actually connected. To do the latter the getPort of > > the TLB and TLB walker for x86 were added to override the BaseTLB that > > returns NULL. > > > > > > Diffs > > ----- > > > > src/arch/alpha/interrupts.hh 241ee47b0dc6 > > src/arch/arm/interrupts.hh 241ee47b0dc6 > > src/arch/mips/interrupts.hh 241ee47b0dc6 > > src/arch/power/interrupts.hh 241ee47b0dc6 > > src/arch/sparc/interrupts.hh 241ee47b0dc6 > > src/arch/x86/interrupts.hh 241ee47b0dc6 > > src/arch/x86/interrupts.cc 241ee47b0dc6 > > src/arch/x86/pagetable_walker.hh 241ee47b0dc6 > > src/arch/x86/tlb.hh 241ee47b0dc6 > > src/arch/x86/tlb.cc 241ee47b0dc6 > > src/cpu/base.cc 241ee47b0dc6 > > > > Diff: http://reviews.gem5.org/r/1062/diff/ > > > > > > Testing > > ------- > > > > util/regress all passing (disregarding t1000 and eio) > > > > > > Thanks, > > > > Andreas Hansson > > > > > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > -- Regards, Ankita _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
