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Do you have any results showing that this is actually faster than the current code? Since it's purely a performance optimization, it seems like that should be a prerequisite. src/arch/x86/tlb.cc <http://reviews.gem5.org/r/1143/#comment2913> This whole algorithm here is (1) a bit inscrutable and (2) looks potentially inefficient. (1) could be fixed with some comments. Should I be concerned about (2)? src/arch/x86/vtophys.cc <http://reviews.gem5.org/r/1143/#comment2912> same comment here - Steve Reinhardt On April 8, 2012, 1:02 a.m., Gabe Black wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1143/ > ----------------------------------------------------------- > > (Updated April 8, 2012, 1:02 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8945:f40e80105a03 > --------------------------- > X86: Use the AddrTrie class to implement the TLB. > > This change also adjusts the TlbEntry class so that it stores the number of > address bits wide a page is rather than its size in bytes. In other words, > instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K, > but it's a little harder going the other way. > > > Diffs > ----- > > src/arch/x86/pagetable.hh a47fd7c2d44e > src/arch/x86/pagetable.cc a47fd7c2d44e > src/arch/x86/pagetable_walker.hh a47fd7c2d44e > src/arch/x86/pagetable_walker.cc a47fd7c2d44e > src/arch/x86/tlb.hh a47fd7c2d44e > src/arch/x86/tlb.cc a47fd7c2d44e > src/arch/x86/vtophys.cc a47fd7c2d44e > > Diff: http://reviews.gem5.org/r/1143/diff/ > > > Testing > ------- > > > Thanks, > > Gabe Black > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
