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(Updated April 14, 2012, 11:33 p.m.) Review request for Default. Description (updated) ------- Changeset 8953:488d45aeb672 --------------------------- X86: Use the AddrTrie class to implement the TLB. This change also adjusts the TlbEntry class so that it stores the number of address bits wide a page is rather than its size in bytes. In other words, instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K, but it's a little harder going the other way. Diffs (updated) ----- src/arch/x86/pagetable.hh 6188362beee1 src/arch/x86/pagetable.cc 6188362beee1 src/arch/x86/pagetable_walker.hh 6188362beee1 src/arch/x86/pagetable_walker.cc 6188362beee1 src/arch/x86/tlb.hh 6188362beee1 src/arch/x86/tlb.cc 6188362beee1 src/arch/x86/vtophys.cc 6188362beee1 Diff: http://reviews.gem5.org/r/1143/diff/ Testing ------- Thanks, Gabe Black _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
